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U PAS A User Friendly ADC Simulator for Courses on Analog Design Bibhu Datta Sahoo and Behzad Razavi Electrical Engineering Department University of California Los Angeles bsahoo ee ucla edu razavi ee ucla edu II P IPELINED ADC M ODELING I SSUES Abstract A simulator with a graphical user interface has been developed for the analysis and design of pipelined analog to digital converters The user can enter parameters such as resolution per stage number of pipelined stages input and clock frequencies input amplitude op amp nonlinearity capacitor mismatch and comparator offset The simulator then computes various static and dynamic properties of the system such as residue plots differential and integral nonlinearity profiles output spectrum and input referred noise Available as an executable code the simulator can run on various platforms Shown in Fig 1 a a pipelined ADC consists of N stages that concurrently operate on N consecutive samples of the analog input signal Each stage digitizes its input Vin by means of a sub ADC with a resolution of M bits thereby producing a digital estimate of Vin This estimate is then returned to the analog domain by a subdigital to analog converter sub DAC and subtracted from Vin Called the residue the resulting difference is amplified by a factor of 2M and applied to the next stage in the pipeline for finer digitization Most advanced courses on analog design include a detailed treatment of pipelined analog to digital converters ADCs The analysis of this class of ADCs becomes increasingly difficult as various imperfections must be taken into account and their effect must be traced through the stages Similarly the design of pipelined ADCs presents tough challenges as the device and supply scaling exacerbates these imperfections requiring analog simulations that may take hours each time This paper introduces the UCLA Pipelined ADC Simulator U PAS a tool developed in MATLAB during our research on ADCs and subsequently used in our graduate



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