MAIN MENUCD/DVD HelpSearch CD/DVDSearch ResultsPrintAuthor IndexTable of ContentsU-PAS : A User-Friendly ADC Simulator for Courses onAnalog DesignBibhu Datta Sahoo and Behzad RazaviElectrical Engineering DepartmentUniversity of California, Los [email protected],[email protected]—A simulator with a graphical user inter-face has been developed for the analysis and designof pipelined analog-to-digital converters. The usercan enter parameters such as resolution per stage,number of pipelined stages, input and clock frequen-cies, input amplitude, op amp nonlinearity, capacitormismatch, and comparator offset. The simulator thencomputes various static and dynamic properties ofthe system such as residue plots, differential andintegral nonlinearity profiles, output spectrum, andinput-referred noise. Available as an executable code,the simulator can run on various platforms.I. INTRODUCTIONMost advanced courses on analog design include a de-tailed treatment of pipelined analog-to-digital converters(ADCs). The analysis of this class of ADCs becomesincreasingly difficult as various imperfections must betaken into account and their effect must be traced throughthe stages. Similarly, the design of pipelined ADCspresents tough challenges as the device and supply scal-ing exacerbates these imperfections, requiring “analog”simulations that may take hours each time.This paper introduces the UCLA Pipelined ADCSimulator (U-PAS), a tool developed in MATLAB duringour research on ADCs and subsequently used in ourgraduate course on the design of data converters. Aimingto expand and enhance the students’ understanding ofpipelined ADCs, U-PAS runs orders of magnitude fasterthan circuit simulators. It can therefore readily reveal andquantify the effect of each imperfection in each stage ofthe pipeline. Operating through a simple and efficientgraphical user interface (GUI), the tool performs a com-prehensive analysis based on user-specified parametersand produces various types of output characteristics.Section II of the paper presents the modeling ofpipelined ADCs using an approach that lends itself toefficient simulations. Section III presents the simulatorinterface and Sectio n IV p rovides examples of simulationresults.II. PIPELINED ADC MODELINGISSUESShown in Fig. 1(a), a pipelined ADC consists of Nstages that concurrently operate on N consecutive sam-ples of the analog input signal. Each stage digitizes itsinput, Vin, by means o f a sub-ADC with a resolution ofM bits, thereby producing a digital estimate of Vin.Thisestimate is then returned to the analog domain by a sub-digital-to-analog converter (sub-DAC), and subtractedfrom Vin. Called the “residue”, the resulting differenceis amplified by a factor of 2Mand applied to the nextstage in the pipeline for finer digitization.SubADCSubDAC2MinVVout+_DigitalEstimateEstimateAnalogResidueM(a)inVVREFEstimateAnaloginVVREFResidueVREF4(b)Stage 1Stage 2InputStage NFig. 1. Pipelined ADC architecture.Figure 1(b) plots the analog estimate and the residueas a function of Vin. In this example, the residue ideally77978-1-4244-4406-9/09/$25.00 ©2009 IEEbegins from zero at integer multip les of VREF/4 andlinearly rises to a maximum value of VREF/4. Withdevice and circuit imperfections, on the other hand,the residue plot experiences various distortions. Theprincipal difficulty in the analysis is that the residueplot becomes increasingly complex for stages farther inthe pipeline. As an example, Figure 2 shows a residueplot including the effect of capacitor mismatch andcomparator offset in the third stage of an ADC.−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−0.5−0.4−0.3−0.2−0.100.10.20.30.40.5Stage 3 Input (V)Residue (V)Fig. 2. Residue of third stage of a pipelined ADC.A common type of pipelined ADCs employs a resolu-tion of 1.5 bits per stage because this choice lends itselfto a compact, efficient implementation. Figure 3 depictsa 1.5-bit stage consisting of two comparators (hence theterm “1.5 bits”) and a switched-capacitor multiply-by-2circuit called a multiplying DAC (MDAC) [1].C11Φ1ΦC2Φ2VREF4inVoutVCLXCREFKVD1D1K000111−10+1VREF4+2Φ1Φ−VX1AMDACSub−ADCFig. 3. Pipelined stage with 1.5-bit resolution.The comparators make a coarse decision, placing Vinin one of the three voltage ranges: below −VREF/4,between −VREF/4 and VREF/4, or above VREF/4.TheMDAC subtracts the sub-ADC output from the input bymeans of C1and p roduces the amplified residue.Since op amps realized in deep-submicron CMOStechnology suffer from significant nonlinearity, wemodel the static input-output characteristic of A1in Fig.3asVout≈ α1Vx+ α2V2x+ α3V3x. (1)It can be shown that the total charge on C1and C2inthe sampling mode is given byQsamp=(C1+ C2)Vin− (C1+ C2+ Cx)Vx1, (2)and in amplification mode byQamp= C1KVref+C2Vout− (C1+C2+Cx)Vx2. (3)These equations can be readily solved in Matlab to yieldthe output of each stage in the pipeline.In addition to static characteristics, U-PAS also modelsthe dynamic behavior of each stage in terms of both lin-ear and nonlinear settling. The linear settling componentis based on the small signal model of the MDAC andrepresented by a single time constant [2]:τamp=CL(C1+ Cx)+CLC2+(C1+ Cx)C2Gm. (4)The nonlinear settlin g is modeled by the op amp slewrate, which is calculated from the op amp characteristicsprovided by the user.In high-resolution pipelined ADCs, the kT/C noiseand the op amp noise must be calculated accuratelyfor all of the stages and summed properly to yield thetotal input-referred noise and its effect on the signal-to-(noise+distortion) ratio (SNDR). U-PAS incorporatesa state-space methodology [3] to d etermine the noisecontributed by each stage and hence the overall SNDR.III. SIMULATOR INTERFACEThe U-PAS GUI is shown in Fig. 4. The interfaceaccepts the following parameters:(1) ADC Parameters− The type of architecture and MDAC (1-bit or 1.5-bit stages; “flip-around” or “non-flip-around” MDACtopologies).− The overall resolution.− The input signal amplitude and frequency.(2) Stage Parameters− The gain (a) and second-order and third-order nonlin-earity coefficients (b and c respectively) of the op ampin each stage.− The op amp transconductance.− The capacitors in the MDAC.− The offsets of the comparators.− The parasitic input capacitance of the op amp.− The input-referred offset voltage of the op amp.Upon entering the parameters (or leaving them attheir