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U PAS A User Friendly ADC Simulator for Courses on Analog Design Bibhu Datta Sahoo and Behzad Razavi Electrical Engineering Department University of California Los Angeles bsahoo ee ucla edu razavi ee ucla edu II P IPELINED ADC M ODELING I SSUES Abstract A simulator with a graphical user interface has been developed for the analysis and design of pipelined analog to digital converters The user can enter parameters such as resolution per stage number of pipelined stages input and clock frequencies input amplitude op amp nonlinearity capacitor mismatch and comparator offset The simulator then computes various static and dynamic properties of the system such as residue plots differential and integral nonlinearity profiles output spectrum and input referred noise Available as an executable code the simulator can run on various platforms Shown in Fig 1 a a pipelined ADC consists of N stages that concurrently operate on N consecutive samples of the analog input signal Each stage digitizes its input Vin by means of a sub ADC with a resolution of M bits thereby producing a digital estimate of Vin This estimate is then returned to the analog domain by a subdigital to analog converter sub DAC and subtracted from Vin Called the residue the resulting difference is amplified by a factor of 2M and applied to the next stage in the pipeline for finer digitization Most advanced courses on analog design include a detailed treatment of pipelined analog to digital converters ADCs The analysis of this class of ADCs becomes increasingly difficult as various imperfections must be taken into account and their effect must be traced through the stages Similarly the design of pipelined ADCs presents tough challenges as the device and supply scaling exacerbates these imperfections requiring analog simulations that may take hours each time This paper introduces the UCLA Pipelined ADC Simulator U PAS a tool developed in MATLAB during our research on ADCs and subsequently used in our graduate course on the design of data converters Aiming to expand and enhance the students understanding of pipelined ADCs U PAS runs orders of magnitude faster than circuit simulators It can therefore readily reveal and quantify the effect of each imperfection in each stage of the pipeline Operating through a simple and efficient graphical user interface GUI the tool performs a comprehensive analysis based on user specified parameters and produces various types of output characteristics Section II of the paper presents the modeling of pipelined ADCs using an approach that lends itself to efficient simulations Section III presents the simulator interface and Section IV provides examples of simulation results 978 1 4244 4406 9 09 25 00 2009 IEE Stage 1 Input I INTRODUCTION Stage 2 Stage N Residue V in 2 Sub ADC Sub DAC M Vout Analog Estimate Digital Estimate M Analog Estimate a V REF V in Residue V REF 4 V REF V in b Fig 1 Pipelined ADC architecture Figure 1 b plots the analog estimate and the residue as a function of Vin In this example the residue ideally 77 begins from zero at integer multiples of VREF 4 and linearly rises to a maximum value of VREF 4 With device and circuit imperfections on the other hand the residue plot experiences various distortions The principal difficulty in the analysis is that the residue plot becomes increasingly complex for stages farther in the pipeline As an example Figure 2 shows a residue plot including the effect of capacitor mismatch and comparator offset in the third stage of an ADC model the static input output characteristic of A1 in Fig 3 as Vout 1 Vx 2 Vx2 3 Vx3 1 It can be shown that the total charge on C1 and C2 in the sampling mode is given by Qsamp C1 C2 Vin C1 C2 Cx Vx1 and in amplification mode by Qamp C1 KVref C2 Vout C1 C2 Cx Vx2 3 0 5 0 4 These equations can be readily solved in Matlab to yield the output of each stage in the pipeline In addition to static characteristics U PAS also models the dynamic behavior of each stage in terms of both linear and nonlinear settling The linear settling component is based on the small signal model of the MDAC and represented by a single time constant 2 0 3 Residue V 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 Stage 3 Input V Fig 2 CL C1 Cx CL C2 C1 Cx C2 4 Gm The nonlinear settling is modeled by the op amp slew rate which is calculated from the op amp characteristics provided by the user In high resolution pipelined ADCs the kT C noise and the op amp noise must be calculated accurately for all of the stages and summed properly to yield the total input referred noise and its effect on the signalto noise distortion ratio SNDR U PAS incorporates a state space methodology 3 to determine the noise contributed by each stage and hence the overall SNDR amp Residue of third stage of a pipelined ADC A common type of pipelined ADCs employs a resolution of 1 5 bits per stage because this choice lends itself to a compact efficient implementation Figure 3 depicts a 1 5 bit stage consisting of two comparators hence the term 1 5 bits and a switched capacitor multiply by 2 circuit called a multiplying DAC MDAC 1 MDAC 2 1 C2 1 C1 V in 1 III S IMULATOR I NTERFACE VX CX A1 The U PAS GUI is shown in Fig 4 The interface accepts the following parameters 1 ADC Parameters The type of architecture and MDAC 1 bit or 1 5bit stages flip around or non flip around MDAC topologies The overall resolution The input signal amplitude and frequency 2 Stage Parameters The gain a and second order and third order nonlinearity coefficients b and c respectively of the op amp in each stage The op amp transconductance The capacitors in the MDAC The offsets of the comparators The parasitic input capacitance of the op amp The input referred offset voltage of the op amp Upon entering the parameters or leaving them at their default values the user can perform the following analyses 1 Static Characteristics Vout CL 2 D1 KVREF V REF D1 K 4 00 1 01 0 11 1 V REF 4 Sub ADC Fig 3 2 Pipelined stage with 1 5 bit resolution The comparators make a coarse decision placing Vin in one of the three voltage ranges below VREF 4 between VREF 4 and VREF 4 or above VREF 4 The MDAC subtracts the sub ADC output from the input by means of C1 and produces the amplified residue Since op amps realized in deep submicron CMOS technology suffer from significant nonlinearity we 78 DNLPlot 1 DNL LSB 0 5 0 0 5 1 50 100 150 200 250 Code INL Plot 4 INL LSB 2 0 2 4 0 100 200 300 Code Fig 4 U PAS


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