Main PageISLPED'00Front MatterTable of ContentsSession IndexAuthor Index114 New Clock-Gating Techniques for Low-Power Flip-flops A.G.M. Strollo, E. Napoli, D. De Caro University of Naples "Federico II" Department of Electronic and Telecommunication Engineering via Claudio, 21 - Naples - Italy +39-0817683125 Email: [email protected] ABSTRACT Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application. Keywords CMOS digital integrated circuits, flip-fops, low-power circuits, transition probability. 1. INTRODUCTION Low-power techniques are essential in modern VLSI design due to the continuous increase of clock frequency and chip complexity [3]. Various recently proposed techniques yield low power operation reducing signals switching activity [1,4,15]. Such techniques are generally applied to internal nodes with high capacitive load that heavily contribute to total power dissipation. In particular, the clock system, composed by flip-flops and clock distribution network, is one of the most power consuming subsystem in a VLSI circuit [13]. As a consequence many techniques have been proposed to reduce clock system power dissipation [5,11,12]. Disabling the clock signal (clock gating) in inactive portions of the chip is a useful approach for power dissipation reduction. Clock gating can be applied to different hierarchical levels. It is possible to disable the clock signal that drive a big functional unit reducing power dissipation on both its internal nodes and its clock line [14]. Other papers use clock gating with lower granularity level [2,9]. In these cases a single circuitry that enables the activity of a whole set of flip-flops is presented. Recently it has been shown that clock gating can be successfully applied when a different activation function is generated for each flip-flop [6,8]. Papers [6,8] show that sensible reduction of power consumption is achieved if flip-flop input signal switching activity is sufficiently low. In such cases each flip-flop includes its own gating logic and hence the introduced overhead must be limited as much as possible. In [6,8] the use of a combinatorial gating logic is proposed. Unfortunately a correct timing of the flip-flop is guaranteed only if the gating logic is sequential. As a consequence the solutions proposed in [6,8] need additional effort to avoid timing violations. In [8] a subnano-pulse generator is used on the clock line while in [6] severe constrains on clock duty-cycle are imposed. Proposed solutions can be hardly used when reliable operation is needed (as in the design of leaf cells) since they impose severe timing constrains. In this paper, two novel low power flip-flops will be presented. Proposed flip-flops use gating techniques to gain low power operation and show no limitation on clock duty cycle. The first technique [11], named as Double Gating in the following, applies gating technique not to the whole flip-flop, but separately to the master latch and to the slave latch. Although, in this way, the introduced overhead is doubled, it will be shown that significant power dissipation reduction is obtained if input signal switching activity is low. The second technique, named as NC2MOS Gating in the following, uses one only gating logic for the whole flip-flop. The gating logic is sequential with reduced overhead. Operation principle for Double Gating and NC2MOS Gating will be presented in sections II and III. Simulation results for flip-flops designed up to the layout level will be presented in section IV. Performance of a 16-bit counter realized with proposed flip-flops is presented in section V. 2. GATING BOTH MASTER AND SLAVE LATCHES (DOUBLE GATING) The schematic of a gated latch is shown in Figure 1. The latch is positive level-sensitive (it is transparent when ckg=1 and in hold for ckg=0). The comparison between D and Q is performed by a XOR gate, while the gating logic is a simple AND gate. The operation of the circuit is as follows. If ck is 0, then ckg is also 0 and the latch is correctly in hold state. On the other hand, when ck is high and D is different from Q, the gating logic enables the ckg signal so that the latch can correctly switch. Note that if D is equal to Q the gating logic inhibits the propagation of switching activity from ck to ckg. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED ’00, Rapallo, Italy. Copyright 2000 ACM 1-58113-190-9/00/0007…$5.00.115 A negative level-sensitive clock-gated latch is quite similar to the schematic of Figure 1. The difference is in the gating logic (implemented with an OR gate) and in the comparator logic (implemented with a XNOR gate). With reference to power dissipation let us firstly examine the case with input signal switching activity, α, equal zero. In this case a power consumption reduction is obtained if the capacitive load introduced on the clock line by the gating logic (CCk), is lower than the capacitance on the ckg node (CCkg). When α increases, power consumption overhead introduced by the comparator and the gating logic also increases. Let us define αlim as the switching activity value that provides equal power dissipation for gated and no gated latches. For α > αlim gated latches are useless as they provide higher power dissipation. This is a common characteristics of gated latches and flip-flops that, therefore, are best suited for applications in which data switching activity is low [6,8,11]. It is worth noting that the approach shown in Figure 1 can not be applied to an edge-triggered flip-flop. In this case, in fact, a change of D while ck is high causes a commutation of ckg, triggering the flip-flop. In previous papers the problem with