WUSTL CSE 465M - LEON2 Processor User’s Manual (92 pages)

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LEON2 Processor User’s Manual



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LEON2 Processor User’s Manual

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Pages:
92
School:
Washington University in St. Louis
Course:
Cse 465m - Digital Systems Laboratory
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LEON2 XST User s Manual LEON2 Processor User s Manual XST Edition Version 1 0 30 July 2005 GAISLER RESEARCH 2 LEON2 XST User s Manual Copyright 2005 Gaisler Research Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying provided also that the entire resulting derived work is distributed under the terms of a permission notice identical to this one Permission is granted to copy and distribute translations of this manual into another language under the above conditions for modified versions GAISLER RESEARCH LEON2 XST User s Manual 1 1 1 1 2 1 3 1 4 1 4 1 1 4 2 1 4 3 1 4 4 1 4 5 1 4 6 1 4 7 1 4 8 1 4 9 1 4 10 1 4 11 1 4 12 1 4 13 1 4 14 1 4 15 1 5 Introduction Overview License Fault tolerant LEON LEON FT Functional overview Integer unit Floating point unit and co processor Cache sub system Memory management unit Debug support unit Memory interface Timers Watchdog UARTs Interrupt controller Parallel I O port AMBA on chip buses PCI interface Ethernet MAC On chip ram Performance 8 8 8 8 9 9 9 9 10 10 10 10 10 10 10 10 11 11 11 11 11 2 2 1 2 2 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 3 7 2 3 8 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 Simulation and synthesis Un packing the tar file Configuration Simulation Compilation of the model Generic test bench Disassembler Modelsim support Ncsim support GNU VHDL GHDL support Synopsys VSS support Post synthesis simulation Synthesis General Synplify Synopsys DC Xilinx XST Synthesis board support packages 12 12 12 12 12 13 13 14 14 14 14 14 15 15 15 15 16 16 3 3 1 3 2 LEON integer unit 18 Overview 18 Instruction pipeline 19 GAISLER RESEARCH LEON2 XST User s Manual 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 10 1 3 10 2 3 10 3 3 10 4 3 10 5 Multiply instructions Multiply and accumulate instructions Divide instructions Processor reset operation Exceptions Hardware breakpoints SPARC Implementor s ID Floating point unit Introduction Gaisler Research s floating point unit GRFPU The Meiko FPU The LTH FPU Generic co processor 19 20 20 20 21 22 22 22 22 22 23 23 23 4 4 1 4 2 4 2 1 4 2 2 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 4 4 5 4 6 4 7 4 7 1 4 7 2 4 8 Cache sub system Overview Instruction cache Operation Instruction cache tag Data cache Operation Write buffer Data cache snooping Data cache tag Cache flushing Diagnostic cache access Cache line locking Local ram Local instruction ram Local data ram Cache Control Register 24 24 25 25 25 26 26 26 27 27 27 28 28 29 29 29 29 5 5 1 5 2 5 3 5 4 Memory management unit ASI mappings Caches MMU registers Translation look aside buffer TLB 31 31 31 31 32 6 6 1 6 2 6 3 6 4 AMBA on chip buses Overview AHB bus APB bus AHB transfers generated by the processor 33 33 33 33 33 GAISLER RESEARCH LEON2 XST User s Manual 7 7 1 7 2 7 2 1 7 2 2 7 2 3 7 3 7 3 1 7 3 2 7 4 7 4 1 7 4 2 7 5 7 5 1 7 5 2 7 5 3 7 5 4 7 5 5 7 5 6 7 6 7 7 7 8 7 9 7 10 On chip peripherals On chip registers Interrupt controller Operation Interrupt assignment Control registers Secondary interrupt controller Operation Control registers Timer unit Operation Registers UARTs Transmitter operation Receiver operation Baud rate generation Loop back mode Interrupt generation UART registers Parallel I O port LEON configuration register Power down AHB status register AHB ram 34 34 35 35 36 36 38 38 39 40 40 41 42 42 43 43 43 44 44 45 47 47 48 48 8 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 9 1 8 9 2 8 9 3 8 9 4 8 9 5 8 9 6 8 9 7 8 9 8 External memory access Memory interface Memory controller PROM access Memory mapped I O SRAM access Burst cycles 8 bit and 16 bit PROM and SRAM access 8 and 16 bit I O access SDRAM access General Address mapping Initialisation Configurable SDRAM timing parameters Refresh SDRAM commands Read cycles Write cycles 49 49 49 50 50 51 52 52 53 53 53 53 54 54 54 54 54 55 GAISLER RESEARCH LEON2 XST User s Manual 8 9 9 8 9 10 8 10 8 11 8 12 8 13 8 14 8 15 8 16 Address bus connection Clocking Memory configuration register 1 MCFG1 Memory configuration register 2 MCFG2 Memory configuration register 3 MCFG3 Write protection Using BRDYN Access errors Attaching an external DRAM controller 55 55 55 56 57 57 57 58 58 9 PCI interface 59 10 Ethernet interface 60 11 11 1 11 2 11 2 1 11 2 2 11 2 3 11 2 4 11 2 5 11 2 6 11 3 11 3 1 11 3 2 11 3 3 11 3 4 11 4 11 4 1 11 4 2 11 4 3 11 4 4 11 5 11 6 11 7 Hardware debug support Overview Debug support unit Overview Trace buffer DSU memory map DSU control register DSU breakpoint registers DSU trap register DSU communication link Operation DSU UART control register DSU UART status register Baud rate generation Common operations Instruction breakpoints Single stepping Alternative debug sources Booting from DSU Design limitations DSU monitor External DSU signals 61 61 61 61 62 64 65 66 66 67 67 68 68 69 69 69 70 70 70 70 70 70 12 12 1 12 2 12 3 Signals Memory bus signals System interface signals Signal description 72 72 72 73 13 13 1 VHDL model architecture 76 Model hierarchy 76 GAISLER RESEARCH LEON2 XST User s Manual 13 2 13 3 13 3 1 13 3 2 13 3 3 13 3 4 13 4 13 4 1 13 4 2 Model coding style AMBA buses AMBA AHB AHB cache aspects AHB protection signals APB bus Floating point unit and co processor Generic CP interface FPU interface 77 78 78 79 79 79 79 79 80 14 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 8 1 14 8 2 14 8 3 …


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