1 Introduction1.1 Overview1.2 License1.3 Fault-tolerant LEON (LEON-FT)1.4 Functional overview1.4.1 Integer unit1.4.2 Floating-point unit and co-processor1.4.3 Cache sub-system1.4.4 Memory management unit1.4.5 Debug support unit1.4.6 Memory interface1.4.7 Timers1.4.8 Watchdog1.4.9 UARTs1.4.10 Interrupt controller1.4.11 Parallel I/O port1.4.12 AMBA on-chip buses1.4.13 PCI interface1.4.14 Ethernet MAC1.4.15 On-chip ram1.5 Performance2 Simulation and synthesis2.1 Un-packing the tar-file2.2 Configuration2.3 Simulation2.3.1 Compilation of the model2.3.2 Generic test bench2.3.3 Disassembler2.3.4 Modelsim support2.3.5 Ncsim support2.3.6 GNU VHDL (GHDL) support2.3.7 Synopsys VSS support2.3.8 Post-synthesis simulation2.4 Synthesis2.4.1 General2.4.2 Synplify2.4.3 Synopsys-DC2.4.4 Xilinx XST2.4.5 Synthesis board support packages3 LEON integer unit3.1 Overview3.2 Instruction pipeline3.3 Multiply instructions3.4 Multiply and accumulate instructions3.5 Divide instructions3.6 Processor reset operation3.7 Exceptions3.8 Hardware breakpoints3.9 SPARC Implementor’s ID3.10 Floating-point unit3.10.1 Introduction3.10.2 Gaisler Research’s floating-point unit (GRFPU)3.10.3 The Meiko FPU3.10.4 The LTH FPU3.10.5 Generic co-processor4 Cache sub-system4.1 Overview4.2 Instruction cache4.2.1 Operation4.2.2 Instruction cache tag4.3 Data cache4.3.1 Operation4.3.2 Write buffer4.3.3 Data cache snooping4.3.4 Data cache tag4.4 Cache flushing4.5 Diagnostic cache access4.6 Cache line locking4.7 Local ram4.7.1 Local instruction ram4.7.2 Local data ram4.8 Cache Control Register5 Memory management unit5.1 ASI mappings5.2 Caches5.3 MMU registers5.4 Translation look-aside buffer (TLB)6 AMBA on-chip buses6.1 Overview6.2 AHB bus6.3 APB bus6.4 AHB transfers generated by the processor7 On-chip peripherals7.1 On-chip registers7.2 Interrupt controller7.2.1 Operation7.2.2 Interrupt assignment7.2.3 Control registers7.3 Secondary interrupt controller7.3.1 Operation7.3.2 Control registers7.4 Timer unit7.4.1 Operation7.4.2 Registers7.5 UARTs7.5.1 Transmitter operation7.5.2 Receiver operation7.5.3 Baud-rate generation7.5.4 Loop back mode7.5.5 Interrupt generation7.5.6 UART registers7.6 Parallel I/O port7.7 LEON configuration register7.8 Power-down7.9 AHB status register7.10 AHB ram8 External memory access8.1 Memory interface8.2 Memory controller8.3 PROM access8.4 Memory mapped I/O8.5 SRAM access8.6 Burst cycles8.7 8-bit and 16-bit PROM and SRAM access8.8 8- and 16-bit I/O access8.9 SDRAM access8.9.1 General8.9.2 Address mapping8.9.3 Initialisation8.9.4 Configurable SDRAM timing parameters8.9.5 Refresh8.9.6 SDRAM commands8.9.7 Read cycles8.9.8 Write cycles8.9.9 Address bus connection8.9.10 Clocking8.10 Memory configuration register 1 (MCFG1)8.11 Memory configuration register 2 (MCFG2)8.12 Memory configuration register 3 (MCFG3)8.13 Write protection8.14 Using BRDYN8.15 Access errors8.16 Attaching an external DRAM controller9 PCI interface10 Ethernet interface11 Hardware debug support11.1 Overview11.2 Debug support unit11.2.1 Overview11.2.2 Trace buffer11.2.3 DSU memory map11.2.4 DSU control register11.2.5 DSU breakpoint registers11.2.6 DSU trap register11.3 DSU communication link11.3.1 Operation11.3.2 DSU UART control register11.3.3 DSU UART status register11.3.4 Baud rate generation11.4 Common operations11.4.1 Instruction breakpoints11.4.2 Single stepping11.4.3 Alternative debug sources11.4.4 Booting from DSU11.5 Design limitations11.6 DSU monitor11.7 External DSU signals12 Signals12.1 Memory bus signals12.2 System interface signals12.3 Signal description13 VHDL model architecture13.1 Model hierarchy13.2 Model coding style13.3 AMBA buses13.3.1 AMBA AHB13.3.2 AHB cache aspects13.3.3 AHB protection signals13.3.4 APB bus13.4 Floating-point unit and co-processor13.4.1 Generic CP interface13.4.2 FPU interface14 Model Configuration14.1 Synthesis configuration14.2 Integer unit configuration14.3 FPU configuration14.4 Cache configuration14.5 Memory controller configuration14.6 Debug configuration14.7 Peripheral configuration14.8 Boot configuration14.8.1 Booting from internal prom14.8.2 PMON S-record loader14.8.3 Rdbmon14.8.4 Booting from the debug support unit14.9 AMBA configuration14.9.1 AHB configuration14.9.2 APB configuration14.10 PCI configuration15 Porting to a new technology or synthesis tool15.1 General15.2 Target specific mega-cells15.2.1 Integer unit register-file15.2.2 Parallel FPU & co-processor register file15.2.3 Cache ram memory cells15.2.4 Dual-port rams15.2.5 Pads15.2.6 Adding a new technology or synthesis toolLEON2 XST User’s ManualGAISLER RESEARCHLEON2 Processor User’s ManualVersion 1.0.30 July 2005XST EditionLEON2 XST User’s ManualGAISLER RESEARCH- 2 -Copyright 2005 Gaisler Research.Permission is granted to make and distribute verbatim copies of this manual provided the copyrightnotice and this permission notice are preserved on all copies.Permission is granted to copy and distribute modified versions of this manual under the conditionsfor verbatim copying, provided also that the entire resulting derived work is distributed under theterms of a permission notice identical to this one.Permission is granted to copy and distribute translations of this manual into another language, underthe above conditions for modified versions.LEON2 XST User’s ManualGAISLER RESEARCH1 Introduction..................................................................................................... 81.1 Overview......................................................................................................... 81.2 License............................................................................................................ 81.3 Fault-tolerant LEON (LEON-FT)................................................................... 81.4 Functional overview ....................................................................................... 91.4.1 Integer unit...................................................................................................... 91.4.2 Floating-point unit and co-processor.............................................................. 91.4.3 Cache sub-system ........................................................................................... 91.4.4 Memory management unit.............................................................................. 101.4.5 Debug support unit ......................................................................................... 101.4.6 Memory