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Interconnect (1)OverviewTransistors Everywhere…Impact of Interconnect ParasiticsWhy Does This Matter?INTERCONNECTCapacitance: The Parallel-Plate ModelThe Unit Transistor CapacitanceFringing CapacitanceInterwire CapacitanceImpact of Interwire CapacitanceCapacitance Design DateInter-wire Capacitance per unit wire lengthINTERCONNECTWire ResistanceOhms Per SquareResistance of Non-rectangular RegionsExampleOverviewInterconnect ModelsThe Lumped ModelThe Elmore DelayLumped p NetworkRC TreesSummary: Gates + Wires -> RC TreesRC Trees: The Elmore DelayThe Elmore Delay with RC TreesElmore ExampleAnother Elmore ExampleAnother Elmore ExampleElmore Applications1Interconnect (1)Lecture 818-322 Fall 2003Textbook: [4.1-4.4.5][Slides on RC Trees and Elmore delay model adapted from R. Rutenbar, 18-760 “Logic To Layout”, CMU Fall 2001]Overview Interconnect parametersCapacitanceResistance Inductance (much later in the sequel) Electrical wire models Lumped RC modelElmore delay2Transistors Everywhere… Node-centric perspective •Focus on devices and their propertiesNetwork-centric perspective •Focus on interconnects(today) Impact of Interconnect Parasitics• Reduce Reliability• Affect PerformanceClasses of Parasitics• Capacitive• Resistive• Inductive3Why Does This Matter? ProblemDelays on signals due to wires are no longer negligibleModern designs must meet tight timing specifications  Delay modelingSources for delay⌧Delay comes from parasitic loading of the interconnect⌧Depends critically on the exact shape of the wired netAccurate prediction ⌧We’ll use a first-order model INTERCONNECTDealing with Capacitance4Capacitance: The Parallel-Plate ModelSiO2SubstrateLW >> toxHtoxCurrent flowWLC WLtεCoxoxox==[F/m]εεε0rox=εr= dielectric constant (relative permitivity) = 3.9ε0= permitivity of the free space = 8.854·10-12[F/m]εox= 3.5 ·10-11[F/m]The Unit Transistor Capacitance4λLW2λ2λ5λλλSourceDrain2λ2λWLCCoxg=]m[pF/1017)(3510200)-(100108.8543.9 tεC2410--12oxoxoxµ−×−=×××==tox= (100 – 200) 10-10[m]λ= 0.5 µm; W = 2 µm, L = 1 µm[fF] 5 [pF]0.0051025.52C4g=≈××=−5Fringing Capacitance In modern technologies W/H is reduced -> the parallel-plate model becomes inaccurate The capacitance between the side-walls of the wires and substrate (fringing capacitance) becomes important W - H/2H+(a)(b)Interwire CapacitanceSubstrateSiO2InsulatorLevel1Level2Creates Cross-talk6Impact of Interwire Capacitance(from [Bakoglu89])Capacitance Design Date From 0.25 micron52271914121212M5 (fringe)38149.16.65.45.45.2M5 (pp)452718151514M4 (fringe)35158.976.86.5M4 (pp)4927201918M3 (fringe)4115109.48.9M3 (pp)45292725M2 (fringe)36171513M2 (pp)544740M1 (fringe)574130M1 (pp)54Poly (fringe)88Poly (pp)M4M3M2M1PolyActiveFieldTop PlateBottom PlateParallel Plate (pp) is in aF/µm2Fringe is in aF/µm7Inter-wire Capacitance per unit wire length For 0.25 micron wires, minimally spaced11585859540Fringe CapacitanceM4M3M2M1PolyINTERCONNECTDealing with Resistance8Wire Resistance WLHR = ρH WLSheet ResistanceRoR1R2Ohms Per SquareSix SquaresThree SquaresIILW9Resistance of Non-rectangular RegionsApproximations derived from solving Poisson’s equation!W1/W2= 1(L/W)eq= 2.56= (1sq + 1sq + 0.56sq)110.56W1W2W1W2W2/W1= 1(L/W)eq= 2.2W1W1W2W2Example100sR = (9 + 2∗ 0.56 squares) * 40 mΩ/ = 404.8 mΩCfringe,g= Perimeter Cfringe = 96.8fF (Perimeter = 2200 µm)Cplate,g= Area Cplate= 3.41pF (Area = 110,000 µm2)Given:R = 40 mΩ/Cfringe= 0.044 fF/µmCplate= 0.031 fF/µm2Determine: the resistance between A and B, the plate and fringe capacitances to ground.10Overview Interconnect parametersCapacitanceResistance  Electrical wire models Lumped RC modelElmore delayInterconnect ModelsSiO2SubstrateLWHtoxCurrent flow11The Lumped Model…RdriverVinVoutVoutdriverCLVout(t) = Vin(1 – e-t /τ) where τ = Rdriver×CLBut, the wire isn’t ideal, it has resistance…The Elmore DelayCNC1C2CiR1R2RiRNRC chain (ladder)12Lumped π NetworkVinVoutRCRCRC…R = Rline/N C = Cline/N tN= N(N+1)/2 (RC)t∞=1/2 (RlineCline)…Voutdriverτ =Rline(Cline/2)This is the π model!Rline1/2Cline1/2ClineRC TreesNote: each of the Rs, Cs in this tree are probably different numbers, since each depends on the geometry of the segment13Summary: Gates + Wires -> RC TreesVintV1V2+-Driving InputDriven loadRC Trees: The Elmore DelayVint+-R1R2R4R3R5123450C1C2C3V0 (1- e-t /τ2)V4V5C4C5V0 (1- e-t /τ1) τ is “the Elmore delay” τ = ΣkCk RikAssume one time constant τ is a good approximation for the actual delay14The Elmore Delay with RC TreesShared resistance among paths from root to nodes k and i5Elmore Example W = 1L = 20W = 1L = 5W = 1L = 2R = r (L/W)C = c (WL)Assume: r = 1 c = 2205522222222203099R0= 20CL= 120CL= 2 + 1 = 3W = 1L = 5W = 1L = 2Note: Since it is symmetric, we need to compute only one path!15τleft (5681)τright (7606)Another Elmore ExampleW = 1L = 20W = 1L = 5W = 1L = 220540222233332065449R0= 20CL= 120W = 1L = 4012345678Another Elmore ExampleW = 1L = 20W = 1L = 5W = 1L = 22050.5222233332075549R0= 20CL= 120W = 10L = 5R smallerC bigger16Elmore Applicationsclock rootFlip Flops Elmore delay is the easiest to compute delay estimatorFairly accurate for symmetric designs Inaccurate for anything else Can be used for layout optimization (e.g. clock trees) For more accuracy, there are more sophisticated


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