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Interconnect 1 Lecture 8 18 322 Fall 2003 Textbook 4 1 4 4 5 Slides on RC Trees and Elmore delay model adapted from R Rutenbar 18 760 Logic To Layout CMU Fall 2001 Overview Interconnect parameters Capacitance Resistance Inductance much later in the sequel Electrical wire models Lumped RC model Elmore delay 1 Transistors Everywhere Node centric perspective Focus on devices and their properties Network centric perspective Focus on interconnects today Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 2 Why Does This Matter Problem Delays on signals due to wires are no longer negligible Modern designs must meet tight timing specifications Delay modeling Sources for delay Delay comes from parasitic loading of the interconnect Depends critically on the exact shape of the wired net Accurate prediction We ll use a first order model INTERCONNECT Dealing with Capacitance 3 Capacitance The Parallel Plate Model Current flow L W tox C ox WL C ox WL t ox ox r 0 F m H tox SiO 2 Substrate r dielectric constant relative permitivity 3 9 0 permitivity of the free space 8 854 10 12 F m ox 3 5 10 11 F m The Unit Transistor Capacitance 5 4 C g C ox WL 2 W tox 100 200 10 10 m 0 5 m W 2 m L 1 m 2 2 Source L C ox 2 Drain ox 3 9 8 854 10 12 35 17 10 4 pF m2 t ox 100 200 10 10 C g 2 25 5 10 4 0 005 pF 5 fF 4 Fringing Capacitance In modern technologies W H is reduced the parallel plate model becomes inaccurate The capacitance between the side walls of the wires and substrate fringing capacitance becomes important a H W H 2 b Interwire Capacitance Level2 Insulator Level1 SiO2 Substrate Creates Cross talk 5 Impact of Interwire Capacitance from Bakoglu89 Capacitance Design Date From 0 25 micron Field Parallel Plate pp is in aF m2 Fringe is in aF m Bottom Plate Active Poly M1 M2 M3 M4 Poly pp 88 Poly fringe 54 Top Plate M1 pp 30 41 57 M1 fringe 40 47 54 M2 pp 13 15 17 36 M2 fringe 25 27 29 45 M3 pp 8 9 9 4 10 15 41 M3 fringe 18 19 20 27 49 M4 pp 6 5 6 8 7 8 9 15 35 M4 fringe 14 15 15 18 27 45 M5 pp 5 2 5 4 5 4 6 6 9 1 14 38 M5 fringe 12 12 12 14 19 27 52 6 Inter wire Capacitance per unit wire length For 0 25 micron wires minimally spaced Poly Fringe 40 Capacitance M1 M2 M3 M4 95 85 85 115 INTERCONNECT Dealing with Resistance 7 Wire Resistance R L HW Sheet Resistance Ro L H R1 W R2 Ohms Per Square L I I W Six Squares Three Squares 8 Resistance of Non rectangular Regions Approximations derived from solving Poisson s equation W1 0 56 1 W2 1 W2 W1 W2 1 L W eq 2 56 W2 W1 W1 W2 W1 W2 W1 1 L W eq 2 2 1sq 1sq 0 56sq Example Given R 40 m Cfringe 0 044 fF m Cplate 0 031 fF m2 100 s Determine the resistance between A and B the plate and fringe capacitances to ground R 9 2 0 56 squares 40 m 404 8 m Cfringe g Perimeter Cfringe 96 8fF Perimeter 2200 m Cplate g Area Cplate 3 41pF Area 110 000 m2 9 Overview Interconnect parameters Capacitance Resistance Electrical wire models Lumped RC model Elmore delay Interconnect Models Current flow L W H tox SiO 2 Substrate 10 The Lumped Model Rdriver Vout Vout CL Vin driver Vout t Vin 1 e t where Rdriver CL But the wire isn t ideal it has resistance The Elmore Delay R2 R1 C1 Ri C2 Ci RN CN RC chain ladder 11 Lumped Network Vout Vin R R C C R C Vout driver R Rline N C Cline N tN N N 1 2 RC This is the model t 1 2 RlineCline Rline 1 2Cline 1 2Cline Rline Cline 2 RC Trees Note each of the Rs Cs in this tree are probably different numbers since each depends on the geometry of the segment 12 Summary Gates Wires RC Trees V1 Vin t V2 Driving Input Driven load RC Trees The Elmore Delay 2 Vin 0 4 C4 C2 R2 t R4 V4 V0 1 e t 1 V5 V0 1 e t 2 R1 1 C1 R3 C3 3 5 R5 C5 is the Elmore delay k Ck Rik Assume one time constant is a good approximation for the actual delay 13 The Elmore Delay with RC Trees 5 Shared resistance among paths from root to nodes k and i Elmore Example 20 R0 20 W 1 L 20 W 1 L 5 W 1 L 2 20 20 W 1 L 5 5 W 1 L 2 CL 1 R r L W C c WL Assume r 1 c 2 9 2 2 2 30 5 2 2 2 2 9 2 CL 2 1 3 Note Since it is symmetric we need to compute only one path 14 Another Elmore Example 20 R0 20 1 W 1 L 20 20 20 2 W 1 L 40 W 1 L 5 5 4 W 1 L 2 9 3 2 2 3 3 2 2 7 8 CL 1 65 40 6 3 44 5 3 right left 7606 5681 Another Elmore Example 20 R0 20 W 1 L 20 W 1 L 5 R smaller C bigger 20 20 W 10 L 5 5 W 1 L 2 9 CL 1 2 2 3 75 0 5 3 2 2 3 54 3 15 Elmore Applications Elmore delay is the easiest to compute delay estimator clock root Fairly accurate for symmetric designs Inaccurate for anything else Can be used for layout optimization e g clock trees Flip Flops For more accuracy there are more sophisticated models 16


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