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Statistic Counter for Networking Hardware Modules



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Statistic Counter for Networking Hardware Modules Michael Attig John W Lockwood Department of Computer Science Applied Research Lab Washington University 1 Brookings Drive Box 1045 Saint Louis MO 63130 WUCS 2002 20 http www arl wustl edu arl projects fpx July 17 2002 Abstract Hundreds of types of events can occur in a complex networking device and millions of these events occur every second In order to debug and manage a complex networking device it is necessary to count events and track statistics A device has been implemented that counts 256 events from three independent sources The module provides a simple interface to read back the number of occurrences of each event To most efficiently utilize the area on the chip the counting module stores the counter values in block memory on a FPGA device rather than in flip flops 1 1 Introduction Tracking events is a key method for debugging network hardware The circuit described in this report provides a simple increment pulse and counter number interface to track statistics in field programmable gate array FPGA hardware Originally designed to be placed within the Control Cell Processor CCP 1 of the FPX 2 3 4 the statistics counter can also be used to interface with a wide range or other network hardware modules The statistics counter utilizes fully synchronous design All transfers of data and state transitions occur on the rising edge of the clock In addition the design is isolated from external modules by flip flops on all inputs and outputs excluding clock The statistics counter has run through simulation with ModelSim and it has been synthesized with the Xilinx back end tools The statistics counter can operate at a clock frequency of 76 25 MHz encompassing only 1 of the Xilinx 2000E 6 FG680 The statistics counter has been integrated into the CCP allowing control cells to initiate up to four counter reads 2 Interface The statistics counter is intended to be instantiated by an exterior module that will generate the increment read signals and supply the counter number A strobed increment read pulse and counter number inform the statistics counter to increment read the specified counter number As shown in Figure 1 there are ten inputs and three outputs to the statistics counter inc cntr isar inc cntr osar inc cntr qm cntr read cntr num isar cntr num osar cntr num qm cntr num read 8 CCP Statistics Counter Module 32 reset l clk data strobe cntr data ready Figure 1 The Statistics Counting Module Interface Inputs are on the left and outputs are on the right The supplied counter numbers are 8 bits wide while the counter value that is returned via cntr data is 32 bits 2 To be used with the CCP the statistics counter required three separate increment signals one to go with each type of event that can occur in the Multi Service Router MSR The MSR generates count events for Input Segmentation and Reassembly ISAR Output Segmentation and Reassembly OSAR and Queue Manager QM 1 3 3 1 Signal Specifications Input Signals When the input signals inc cntr isar inc cntr osar inc cntr qm and cntr read pulse the corresponding 8 bit counter number must have a valid counter number Note that if a counter number is in use by ISAR then it is expected that OSAR and QM will not utilize the same counter number The same holds for OSAR and QM counter numbers An individual increment or read signal cannot pulse on every clock edge In order to be able to service four distinct events an individual signal can only pulse once every four clock ticks This enables the statistics counter to be able to initiate service for each event The four pulse signals inc cntr isar inc cntr osar inc cntr qm and cntr read can pulse at any time relative to each other so long as the same signal pulse is separated by four clock cycles 3 2 Output Signals The output ready is used to specify when the statistics counter is configured to begin counting events The statistics counter will not be configured until reset l has been de asserted for 256 clock ticks During these 256 ticks the statistics counter resets all the counter values to 0 The other outputs provide the read interface to exterior modules Depending on when the cntr read input was pulsed the counter value will be returned within three to six clock ticks following the pulse Valid counter data is signaled by the assertion of data strobe The exterior module needs to latch the value on cntr data when data strobe is asserted 3 3 Example The following example shown in Figure 2 shows one way that increment and read pulses could occur Note that when an increment or read is requested the counter number is supplied on the corresponding 8 bit 3 cntr num line For example if inc cntr isar was pulsed the corresponding ISAR counter number would arrive on the input cntr num isar clk inc cntr isar cntr num isar 12 12 inc cntr osar cntr num osar 25 32 inc cntr qm cntr num qm 41 44 cntr read cntr num read 12 Figure 2 An example of how a increment is initiated In the second clock tick inc cntr isar pulses meaning that one of the ISAR counters in this case 0x12 needs to be incremented Inc cntr qm also pulses in clock tick two and counter number 0x41 is to be incremented In clock tick three inc cntr osar pulses indicating that OSAR counter number 0x25 is to incremented In clock tick six inc cntr isar pulses again Note that this is the earliest that inc cntr isar could have pulsed again In clock tick seven inc cntr osar inc cntr qm and cntr read pulse and each gives their respective counter numbers 4 Architecture The statistics counter is implemented using three files cntr ram vhd cntr fsm vhd and ccp cntr vhd Cntr ram vhd describes the usage of the dualport block RAMs located on the FPGA The cntr fsm vhd file describes the finite state machine FSM used to service increment and read requests Ccp cntr vhd wires up the block RAMs and FSM and it describes multiplexors flip flops counters and increment logic Refer to Figure 3 for a top level block diagram of the statistics counter 4 1 Dualport Block RAM Two dualport block RAMs are used by the statistics counter One contains the upper 16 bits of the 32 bit counter value and the other contains the lower 16 bits Each RAM is 16 by 256 Port A is used as the read 4 cntr num isar 8 8 bit Flip Flops cntr num osar cntr num qm 8 Addr addra 16 cntr num read addrb dout din 16 Upper Block RAM inc cntr isar inc cntr osar Inc Pulse Flip Flops inc cntr qm cntr read 256 x 16 Finite State Machine addra 16 ready addrb dout Q D


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