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Statistic Counter for Networking Hardware Modules

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Statistic Counter for Networking Hardware ModulesMichael AttigJohn W. LockwoodDepartment of Computer ScienceApplied Research LabWashington University1 Brookings Drive, Box 1045Saint Louis, MO 63130WUCS-2002-20http://www.arl.wustl.edu/arl/projects/fpxJuly 17, 2002AbstractHundreds of types of events can occur in a complex networking device, and millions of these eventsoccur every second. In order to debug and manage a complex networking device, it is necessary to countevents and track statistics. A device has been implemented that counts 256 events from three independentsources. The module provides a simple interface to read back the number of occurrences of each event.To most efficiently utilize the area on the chip , the counting module stores the counter values in blockmemory on a FPGA device rather than in flip-flops.11 IntroductionTracking events is a key method for debugging network hardware. The circuit described in this reportprovides a simple increment pulse and counter number interface to track statistics in field programmablegate array (FPGA) hardware. Originally designed to be placed within the Control Cell Processor (CCP)[1]of the FPX [2] [3] [4], the statistics counter can also be used to interface with a wide range or other networkhardware modules.The statistics counter utilizes fully synchronous design. All transfers of data and state transitions occuron the rising edge of the clock. In addition, the design is isolated from external modules by flip-flops onall inputs and outputs (excluding clock). The statistics counter has run through simulation with ModelSim,and it has been synthesized with the Xilinx back-end tools. The statistics counter can operate at a clockfrequency of 76.25 MHz, encompassing only 1% of the Xilinx 2000E-6-FG680. The statistics counter hasbeen integrated into the CCP, allowing control cells to initiate up to four counter reads.2 InterfaceThe statistics counter is intended to be instantiated by an exterior module that will generate the incre-ment/read signals and supply the counter number. A strobed increment/read pulse and counter numberinform the statistics counter to increment/read the specified counter number. As shown in Figure 1, thereare ten inputs and three outputs to the statistics counter.data_strobecntr_datareadyinc_cntr_isarinc_cntr_osarinc_cntr_qmcntr_readcntr_num_isarcntr_num_osarcntr_num_qmcntr_num_readreset_lclkCCPStatisticsCounterModule832Figure 1: The Statistics Counting Module Interface. Inputs are on the left, and outputs are on the right. Thesupplied counter numbers are 8 bits wide, while the counter value that is returned via cntr data is 32 bits.2To be used with the CCP, the statistics counter required three separate increment signals, one to go witheach type of event that can occur in the Multi Service Router (MSR). The MSR generates count events forInput Segmentation and Reassembly (ISAR), Output Segmentation and Reassembly (OSAR), and QueueManager (QM) [1].3 Signal Specifications3.1 Input SignalsWhen the input signals inc cntr isar, inc cntr osar, inc cntr qm, and cntr read pulse, the corresponding8-bit counter number must have a valid counter number. Note that if a counter number is in use by ISAR,then it is expected that OSAR and QM will not utilize the same counter number. The same holds for OSARand QM counter numbers.An individual increment or read signal cannot pulse on every clock edge. In order to be able to servicefour distinct events, an individual signal can only pulse once every four clock ticks. This enables the statisticscounter to be able to initiate service for each event. The four pulse signals inc cntr isar, inc cntr osar,inc cntr qm, and cntr read can pulse at any time relative to each other so long as the same signal pulse isseparated by four clock cycles.3.2 Output SignalsThe output ready is used to specify when the statistics counter is configured to begin counting events. Thestatistics counter will not be configured until reset l has been de-asserted for 256 clock ticks. During these256 ticks, the statistics counter resets all the counter values to 0.The other outputs provide the read interface to exterior modules. Depending on when the cntr readinput was pulsed, the counter value will be returned within three to six clock ticks following the pulse. Validcounter data is signaled by the assertion of data strobe. The exterior module needs to latch the value oncntr data when data strobe is asserted.3.3 ExampleThe following example, shown in Figure 2, shows one way that increment and read pulses could occur.Note that when an increment or read is requested, the counter number is supplied on the corresponding 8-bit3cntr num line. For example, if inc cntr isar was pulsed, the corresponding ISAR counter number wouldarrive on the input cntr num isar.clkinc_cntr_isar12 12cntr_num_isarinc_cntr_osar3225cntr_num_osarinc_cntr_qm41 44cntr_num_qmcntr_read12cntr_num_readFigure 2: An example of how a increment is initiated. In the second clock tick, inc cntr isar pulses, meaningthat one of the ISAR counters, in this case 0x12, needs to be incremented. Inc cntr qm also pulses in clocktick two, and counter number 0x41 is to be incremented. In clock tick three, inc cntr osar pulses, indicatingthat OSAR counter number 0x25 is to incremented. In clock tick six, inc cntr isar pulses again. Note thatthis is the earliest that inc cntr isar could have pulsed again. In clock tick seven, inc cntr osar, inc cntr qm,and cntr read pulse, and each gives their respective counter numbers.4 ArchitectureThe statistics counter is implemented using three files: cntr ram.vhd, cntr fsm.vhd, and ccp cntr.vhd. Cntr ram.vhddescribes the usage of the dualport block RAMs located on the FPGA. The cntr fsm.vhd file describes thefinite state machine (FSM) used to service increment and read requests. Ccp cntr.vhd wires up the blockRAMs and FSM, and it describes multiplexors, flip-flops, counters, and increment logic. Refer to Figure 3for a top-level block diagram of the statistics counter.4.1 Dualport Block RAMTwo dualport block RAMs are used by the statistics counter. One contains the upper 16 bits of the 32-bitcounter value, and the other contains the lower 16 bits. Each RAM is 16 by 256. Port A is used as the read4Q DdinaddrbaddradoutUpperBlock RAM256 x 16dinaddrbaddradoutLowerBlock RAM256 x 16D QD QD QQ DQ


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