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A CAD Suite for High-Performance FPGA Design



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A CAD Suite for High Performance FPGA Design Brad Hutchings Peter Bellows Joseph Hawkins Scott Hemmert Brent Nelson Mike Rytting Department of Electrical and Computer Engineering Brigham Young University Provo UT 84602 hutch ee byu edu 1 Introduction This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high performance configurable computing applications The basis of this tool suite is JHDL 1 a design tool originally conceived as a way to experiment with Run Time Reconfigured RTR designs However what began as a limited experiment to model RTR designs with Java has evolved into a comprehensive suite of design tools and verification aids with these tools being used successfully to implement high performance applications in Automated Target Recognition ATR sonar beamforming and general image processing on configurable computing systems In response to user demands those students developing configurable computing applications JHDL has been modified and augmented to include a graphical debugging tool that allows designers to simulate debug and hierarchically navigate their designs This tool can generate a schematic view annotated with simulation or execution data provide a waveform view of any desired signals and allows the designer to invoke any public methods implemented by the circuit class via Java reflection a schematic generator that can automatically create a high quality schematic view of a JHDL description an EDIF 2 0 netlist class that generates output compatible with current Xilinx M1 place and route software simulation models and transparent run time support for the Annapolis Microsystems WildForce platform a graphical floorplanner under development that will be used cooperatively with the schematic view to manually floor plan designs Effort sponsored by the Defense Advanced Research Projects Agency DARPA under contract number DABT63 96 C 0047 The U S Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright annotation thereon In addition to these specific design aids JHDL provides a unified design environment where a single user interface can be used for both simulation and execution This allows the designer to request either simulation or execution or a mixture of the two using the exact same commands for both For example within this unified environment commands such as set breakpoint examine variable single step etc are the same whether performing simulation or execution This is a big advantage for designers because they can learn a single debugging environment that works for both simulation and execution in contrast with current systems where execution and simulation environments are distinct and very different Other design views are unified as well for example the schematic view can display either simulated values or values retrieved from the FPGA platform during execution using the same view and interface Much of the flexibility of this environment is due to the dual simulation execution environment supported in the original version of JHDL 1 as reported previously switching between simulation and execution mode is done by simply clicking a radio button in the circuit browser The remainder of the paper briefly reviews the origins of JHDL why JHDL was adopted as a design tool and what additional tools and capabilities were added to JHDL to make it a complete design environment 2 JHDL as an RTR design tool The original focus of JHDL was on Run Time Reconfiguration RTR As originally published in FCCM98 it made the following contributions JHDL used object constructors and destructors to describe circuit structures that dynamically change over time JHDL provided a dual simulation execution environment where a designer could easily switch between either software simulation or hardware execution with a single circuit description JHDL program JHDL supported simultaneous execution of hardware and software those parts of the application that extend JHDL library classes are executed in hardware while those parts written using generic Java classes are executed on the CPU s Java virtual machine This makes it possible to fully integrate an application GUI with a hardware description using a single program to describe both Note that the current version of JHDL continues to support these features in addition to the new capabilities that are outlined in this paper 3 Structural design and FPGAs In its current state JHDL is a structural design environment That being said the first question that enters most people s minds at this point is this in this era of behavioral synthesis why are we still interested in structural design The answer is that when working with FPGAs structural design techniques often still result in circuits that are substantially smaller and faster than those developed using only behavioral synthesis tools In addition for many applications found in the configurable computing arena structural capture is simply a faster easier to learn and more effective way to design an application1 Structural design often improves the performance of configurable computing applications because many FPGA based applications can benefit from manual placement of at least some parts of the design Manual placement often results in either smaller or faster circuits or both Indeed it is still common to see overall improvements of about 2 10x area x speed when a few key performance critical data path elements are manually placed Structural design is key to manual placement Effective manual placement can only be achieved if the overall organization of the circuit is well understood and this is only possible if the designer controls or at least understands how the structure of the circuit is generated For example it is very difficult to manually place circuitry that was generated via purely behavioral synthesis In general the designer will not understand the circuit organization generated by the synthesis tool and as such will not be able to ascertain how circuit modules should be placed to reduce area or length of interconnect Moreover each synthesis run may result in a slightly different circuit structure that renders the previous placement irrelevant thus forcing the 1 This is not an argument for using only structural design tools for FPGAs Rather it is an assertion that there is a place for the right kind of structural design tools in any high performance


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