EE 166: Final Exam NAME: 1Question 1 (20 PTS): Using our process parameters and the circuit below design Vout=Vin=3 Volts.EE 166: Final Exam NAME: 2 Question 2 (10PTS): You have just designed a new three input NOR Gate with an equivalent capacitance of 100fF, and an average propagation delay of 1ns (From “100” to “000”) driving a similar three input NOR gate. Design a circuit that will verify the average propagation delay for this three input NAND going back and forth from the “100” to “000” input states that can be measured with an oscilloscope that only can measure signals whose frequencies are 50MHz and smaller (15PTS.). If each nor gate has an equivalent capacitance of100fF, what is the power used by your circuit (5PTS.).EE 166: Final Exam NAME: 3Question 3 (20PTS): You have completed hand calculations for a circuit, entered it in schematic capture, and run a transient analysis. You find that the circuit is too slow (rise time and fall time are too big) compared to your specification. How do you fix the problem? (5pts) You have laid out your circuit (made a picture of what the circuit would look like under a microscope). What do you do next? (5pts) What does it mean when you have a DRC error? (5pts) What does in mean to have an LVS error? (5pts)EE 166: Final Exam NAME: 4 Question 4 (20PTS): Evaluate the layout below in terms of Area(5pts): Manufacturability(5pts): Reliability(5pts): Routability/Porosity of Metal2(5pts):EE 166: Final Exam NAME: 5Question 5 (20PTS): Using the AOI technique design a CMOS circuit to implement the following logic function: Z=(ABCD+EFG)H Show the PNET and the NNET connected into a circuitEE 166: Final Exam NAME: 6Question 6 (10PTS): Using the Euler path method come up the order of the inputs for the circuit in question 5. Do not do the stick diagram!EE 166: Final Exam NAME: 7Question 7 (30PTS): Calculate setup and hold time for the following DFF. Assume : Wn=Wp=1.5microns Ln=Lp=0.6microns Cgnmos=Cgpmos=3fF and Cdnmos=4fF and Cdmpos=4fFEE 166: Final Exam NAME: 8Question 8 (20PTS): Use the FATBUS technique to layout 7DFFs. Show how you would layout the clock line and place the DFFs to minimize clock skew. You may use a simplified symbol of the DFF and just show the clock connections. Use the H-Tree technique to layout 7DFFs. Show how you would layout the clock line and place the DFFs to minimize clock skew. You may use a simplified symbol of the DFF and just show the clock connections.EE 166: Final Exam NAME: 9Question 9 (10PTS): Using our process parameters: a) Design a Schmitt Trigger Circuit with a low to high trip of 3.25V. b) Design a Schmitt Trigger Circuit with a high to low trip of 1.75V. c) How would you test your design?EE 166: Final Exam NAME: 10Question 10 (10PTS): Find the LVS error: Figure 1: Schematic. Figure 2:
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