Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18InterruptsAn interrupt is an exception, a change of the normal progression, or interruption in the normal flow of program execution. An interrupt is essentially a hardware generated function call.Interrupts are caused by both internal and external sources.An interrupt causes the normal program execution to halt and for the interrupt service routine (ISR) to be executed.At the conclusion of the ISR, normal program execution is resumed at the point where it was last.InterruptsInterrupts should be used for infrequent events (1000's of clock cycles)-keyboard strokes -1ms clock ticks -serial data (USART, SPI, TWI)-analog to digital conversionuC response time to interrupts is very fast-AVR: 4 cycles max-80386: 59 cycles min, 104 cycles max; (0-wait state memory; www.intel.com/design/intarch/technote/2153.htm)If response time is really critical, a “tight” polling loop is used.-polling can be faster than interrupts......, but further processing is on hold! //spin on SPSR bit checking for serial transfer complete while (bit_is_clear(SPSR,SPIF)) {}; da: 77 9b sbis 0x0e, 7 ; 1 or 2 cycles dc: fe cf rjmp .-4 ; 2 cyclesInterruptsInterrupts vs. PollingPolling uses a lot of CPU horsepower-checking whether the peripheral is ready or not-are you ready...yet?!-interrupts use the CPU only when work is to be donePolled code is generally messy and unstructured-big loop with often multiple calls to check and see if peripheral is ready-necessary to keep peripheral from waiting-ISRs concentrate all peripheral code in one place (encapsulation)Polled code leads to variable latency in servicing peripherals-whether if branches are taken or not, timing can vary-interrupts give highly predictable servicing latenciesInterruptsAVR interrupt servicing 1. In response to the interrupt, the CPU finishes any pending instructions and then ceases fetching further instructions. Global Interrupt Enable (GIE) bit is cleared.2. Hardware pushes the program counter on the stack. 3. The CPU fetches the instruction from the interrupt vector table that corresponds to the interrupt. This instruction is usually “jmp, address”. The address is the address of the ISR.00000000 <__vectors>: 0: 0c 94 46 00 jmp 0x8c ; 0x8c <__ctors_end> 4: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 8: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 10: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 14: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 18: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 1c: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 20: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 24: 0c 94 63 00 jmp 0xc6 ; 0xc6 <__bad_interrupt> 28: 0c 94 b4 02 jmp 0x568 ; 0x568 <__vector_10>InterruptsAVR interrupt servicing (cont.)4. The CPU then begins to execute the ISR code. The first part of the ISR is compiler generated code that pushes the status register on the stack as well as any registers that will be used in the ISR. From *.lst file:/***********************************************************************/// timer/counter 1 ISR //When the TCNT1 compare1A interrupt occurs, port F bit 4 is toggled. //This creates the alarm sound from the clock. /***********************************************************************/ISR(TIM1_COMPA_vect){ 538: 1f 92 push r1 ;save reg 53a: 0f 92 push r0 ;save reg 53c: 0f b6 in r0, 0x3f ;put SREG into r0 53e: 0f 92 push r0 ;push SREG onto stack 540: 11 24 eor r1, r1 ;clear r1 542: 8f 93 push r24 ;save reg 544: 9f 93 push r25 ;save reg if (alarm_enable == 1) //toggle port F.4 if button pushedcompiler generated codeuser codeInterruptsAVR interrupt servicing (cont.)5. Just before the ISR is done, compiler generated code pops the saved registers as well as the status register. Then the RETI instruction is executed. This restores the program counter from the stack. Global Interrupt Enable bit gets set again.6. The CPU resumes executing the original instruction stream. 55a: 9f 91 pop r25 ;restore regs 55c: 8f 91 pop r24 ;restore regs 55e: 0f 90 pop r0 ;put SREG back into r0 560: 0f be out 0x3f, r0 ;put r0 into SREG 562: 0f 90 pop r0 ;restore regs 564: 1f 90 pop r1 ;restore regs 566: 18 95 reticompiler generated codeInterruptsAVR interrupt vector table-All interrupts have separate interrupt vectors in the interrupt vector table-Interrupts have priority in accordance with their position in the table.-Lower interrupt vector address have higher priority.-Reset has top priority.InterruptsEnabling interrupts 1. Global Interrupt Enable (GIE) bit must be set in the status register (SREG)Global Interrupt Enable (GIE): This bit must be set for interrupts to be enabled. To set GIE:sei(); //global interrupt enableIt is cleared by hardware after an interrupt has occurred, but may be set again by software [ISR(xxx_vec, ISR_NOBLOCK)] or manually with the sie() to allow nested interrupts.It is set by the RETI instruction to enable subsequent interrupts. This is done automatically by the compiler.InterruptsEnabling interrupts 2. The individual interrupt enable bits must be set in the proper control register.-For example, for timer counter 1, the timer overflow bit (TOV)The interrupt occurs when theTOV1 flag becomes set. Onceyou enter the ISR, it is resetautomatically by hardware.TOIE1 must be set to allowthe TCNT1 over flow bit tocause an interruptInterruptsAvr-libc ISR code generation (from *.lst)The c code:ISR(TIMER1_OVF_vect){ external_count++;}The compiler generated ISR:ISR(TIMER1_OVF_vect) { cc: 1f 92 push r1 ##save r1 ce: 0f 92 push r0 ##save r0 d0: 0f b6 in r0, 0x3f ##put SREG into r0 (SREG=0x3F) d2: 0f 92 push r0 ##push SREG onto stack d4: 11 24 eor r1, r1 ##clear r1 d6: 8f 93 push r24 ##push r24 (its about to be used) external_count++; d8: 80 91 00 01 lds r24, 0x0100 ##load r24 with