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Synthesis Synthesis Challenges Challenges for for NextNextGeneration Generation High Performance High Performance and and High Density High Density PLDs PLDs Jason Cong Songjie Xu Department Department of of Computer Computer Science Science University University of of California California Los Los Angeles Angeles USA USA Aplus Aplus Design Design Technologies Technologies Inc Inc Los Los Angeles Angeles USA USA Outline u u Introduction Introduction u Synthesis Challenges for New Architectures u Synthesis Challenges for High Density and High Performance u Concluding Remarks Slide 2 PLD Industry Growth u Enjoyed the exponential growth as the rest of the semiconductor industry u With an even faster rate 36 07 Annual Growth Rate 1994 1998 40 00 35 00 27 78 24 50 30 00 25 00 15 71 20 00 15 00 10 00 5 00 0 00 Company Industry Semiconductor Industry Slide 3 Altera Intel LSI Logic Introduction Definitions u PLD Programmable Logic Device z CPLD Complex PLD z Extensions of early PAL z Consist of PLA like blocks z Macrocell z FPGA Field Programmable Gate Array z Typically based on look up tables LUTs z Multiple LUTs form a programmable logic block PLB Slide 4 Introduction CPLD u Example Altera MAX 7000 Slide 5 Introduction Macrocell u Example Altera MAX 7000 z Each macrocell has a logic array a product term select matrix and a programmable register Slide 6 Introduction Definitions u PLD Programmable Logic Device z CPLD Complex PLD z Extensions of early PAL z Consist of PLA like blocks z Macrocell z FPGA Field Programmable Gate Array z Typically based on look up tables LUTs z Multiple LUTs form a programmable logic block PLB Slide 7 Introduction FPGA u Example Xilinx XC 4000 Slide 8 Introduction PLB u Xilinx XC 4000 z Each PLB has two 4 LUTs one 3 LUT and 2 FFs Slide 9 Introduction Advance of PLD Architectures Slide 10 1980 s 1980 s 1998 1999 1998 1999 Altera Altera MAX5000 5000 MAX APEX20K 20K APEX Xilinx Xilinx XC2000 2000 XC Virtex Virtex 32 192P terms P terms 32 192 600 3



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