For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEX3 Describing DesignsVHDL constructs are used in writing VHDL design descriptions.Uses of these constructs, how to use existing hardware com-ponents in a design, and how to use VHDL packages tocollect and reuse common design information are importantin writing the descriptions. Familiarize yourself with theseconcepts before you write a design description: VHDL Entities VHDL Constructs Defining Designs Structural DesignVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXVHDL EntitiesVHDL-based designs are composed of entities. An entityrepresents one level of the design hierarchy, and can be acomplete design, an existing hardware component, or aVHDL-defined object.Each design has two parts, the entity specification and thearchitecture. The specification of an entity is its externalinterface. The architecture of an entity is its internal imple-mentation. A design has only one entity specification(interface), but can have multiple architectures (implementa-tions). When an entity is compiled into a hardware design, aconfiguration specifies the architecture to use. An entity’sspecification and architecture can be in separate VHDLsource files, or in one VHDL source file.Example 3–1 shows the entity specification of a simple logicgate (a two-input NAND).Example 3–1 VHDL Entity Specificationentity NAND2 is port(A, B: in BIT; –– Two inputs, A and B Z: out BIT); –– One output, Z = (A and B)’end NAND2;Note:In a VHDL description, two hyphens (––) start a com-ment. Everything from the hyphens to the end of the lineis ignored by VHDL Compiler. The only exceptions arecomments that begin with –– pragma or –– synopsys;these comments are VHDL Compiler directives (seeChapter 11).After an entity statement declares an entity specification,that entity can be used by other entities in a design. Theinternal architecture of an entity determines its function.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXExamples 3–2, 3–3, and 3–4 show three different architecturesfor the entity NAND2. The three examples define equivalentimplementations of NAND2. After optimization and synthesis,they all produce the same circuit, probably a 2-input NANDgate in the target technology. The architecture descriptionstyle you use for this entity depends on your own preferences.Example 3–2 shows how the entity NAND2 can be implement-ed by using two components from a technology library. Theentity inputs A and B are connected to AND gate U0, produc-ing an intermediate signal I. Signal I is then connected toinverter U1, producing the entity output Z.Example 3–2 Structural Architecture for Entity NAND2architecture STRUCTURAL of NAND2 is signal I: BIT; component AND_2 –– From a technology library port(I1, I2: in BIT; O1: out BIT); end component; component INVERT –– From a technology library port(I1: in BIT; O1: out BIT); end component;begin U0: AND_2 port map (I1 => A, I2 => B, O1 => I); U1: INVERT port map (I1 => I, O1 => Z);end STRUCTURAL;VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXExample 3–3 shows how you can define the entity NAND2 byits logical function.Example 3–3 Dataflow Architecture for Entity NAND2architecture DATAFLOW of NAND2 isbegin Z <= A nand B;end DATAFLOW;Example 3–4 shows another implementation of NAND2.Example 3–4 RTL Architecture for Entity NAND2architecture RTL of NAND2 isbegin process(A, B) begin if (A = ’1’) and (B = ’1’) then Z <= ’0’; else Z <= ’1’; end if; end process;end RTL;VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXVHDL ConstructsThe top-level VHDL constructs work together to describe adesign. The description consists ofEntitiesThe interfaces to other designs.ArchitecturesThe implementations of design entities. Architecturesmay specify connection via instantiation to other enti-ties.ConfigurationsThe bindings of entities to architectures.ProcessesCollections of sequentially executed statements. Pro-cesses are declared within architectures.SubprogramsAlgorithms that can be used by more than one architec-ture.PackagesCollections of declarations used by one or more designs.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXEntitiesA VHDL design consists of one or more entities. Entities havedefined inputs and outputs and perform a defined function.Each design has two parts, an entity specification and anarchitecture. The entity specification defines the design’sinputs and outputs, and the architecture determines itsfunction.You can describe a VHDL design in one or more files. Each filecontains entities, architectures, or packages. Packagesdefine global information that can be used by several enti-ties. You can often reuse VHDL design files in later designprojects.Figure 3–1 shows a block diagram of a VHDL design’s hierar-chical organization into files.Figure 3–1 Design Organization VHDL DesignVHDL filesEntity specificationsDeclare the interfaces toentities.ArchitecturesDefine the implementations of entities.PackagesDeclare constants, data types, components, and subprograms used by several designs and/or entities.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXArchitecturesAn architecture determines the function of an entity. Fig-ure 3–2 shows the organization of an architecture. Not allarchitectures contain every construct shown.Figure 3–2 Architecture Organization ArchitectureDeclarationsDeclare signals used to communicate between concurrent statements, and between concurrent statements and the interface ports. DeclareConcurrent StatementsBlocksSignal assignmentsProcedure callsComponent instantiationsProcessesCollect concurrent statementsCompute values and assign them totogether.signals.Invoke a predefined algorithm.Create an instance ofanother entity.Define a new algorithm.types,