CSCI 3753 AnnouncementsComputerOrganizationStored Program Computers and Electronic DevicesProgram SpecificationMachine LanguageThe von Neumann ArchitectureThe ALUControl UnitControl Unit OperationPrimary Memory UnitProcessor ModesKernelsSupervisor and User MemoryProcedure Call and Message Passing Operating SystemsSystem Call Using the trap InstructionA Thread Performing a System CallExamples of Exceptions in Pentium SystemsExamples of ExceptionsExamples of Exceptions in Pentium SystemsThe Device-Controller-Software RelationshipDevice Controller InterfacePerforming a Write OperationCPU-I/O OverlapPolling I/O - Busy WaitingDetermining When I/O is CompleteControl Unit with Interrupt (Hardware)Interrupt Handler (Software)A Race ConditionRevisiting the trap Instruction (Hardware)The Trap Instruction OperationDirect Memory AccessMemory-Mapped I/O: Addressing DevicesIntel System InitializationBootstrappingBootstrappingA Bootstrap Loader ProgramOperating Systems: A Modern Perspective, Chapter 4Slide 4-1Copyright © 2004 Pearson Education, Inc.Chapters 3 and 4:Hardware Support for Operating SystemsCSCI 3753Spring 2005Prof. Rick HanOperating Systems: A Modern Perspective, Chapter 4Slide 4-2Copyright © 2004 Pearson Education, Inc.CSCI 3753 Announcements• Moodle - posted last Tuesday’s lecture• Programming shell assignment 0 due Thursday at 11:55 pm, not 11 am• Homework #1 due next Thursday at 11 am• Read Chapters 3 and 4 in the textbook, skip 4.7 and 4.8Operating Systems: A Modern Perspective, Chapter 4Slide 4-3Copyright © 2004 Pearson Education, Inc.4ComputerOrganizationOperating Systems: A Modern Perspective, Chapter 4Slide 4-4Copyright © 2004 Pearson Education, Inc.Stored Program Computers and Electronic DevicesPatternVariable ProgramJacquard LoomStored Program DeviceFixed Electronic DeviceOperating Systems: A Modern Perspective, Chapter 4Slide 4-5Copyright © 2004 Pearson Education, Inc.Program Specificationint a, b, c, d;. . .a = b + c;d = a - 100;Source; Code for a = b + cload R3,bload R4,cadd R3,R4store R3,a; Code for d = a - 100load R4,=100subtract R3,R4store R3,dAssembly LanguageOperating Systems: A Modern Perspective, Chapter 4Slide 4-6Copyright © 2004 Pearson Education, Inc.Machine Language; Code for a = b + cload R3,bload R4,cadd R3,R4store R3,a; Code for d = a - 100load R4,=100subtract R3,R4store R3,dAssembly Language10111001001100…110111001010000…010100111001100…010111010001100…110111001010000…010100110001100…010111001101100…1Machine LanguageOperating Systems: A Modern Perspective, Chapter 4Slide 4-7Copyright © 2004 Pearson Education, Inc.The von Neumann ArchitectureControl Unit(CU)Central Processing Unit (CPU)DeviceDeviceAddress BusData BusArithmetical Logical Unit(ALU)Primary Memory Unit(Executable Memory)Operating Systems: A Modern Perspective, Chapter 4Slide 4-8Copyright © 2004 Pearson Education, Inc.The ALUload R3,bload R4,cadd R3,R4store R3,aRight OperandR1R2Rn. . .Functional UnitLeft OperandResultStatus RegistersTo/from Primary MemoryOperating Systems: A Modern Perspective, Chapter 4Slide 4-9Copyright © 2004 Pearson Education, Inc.Control Unit3046305030543058Primary MemoryFetch UnitFetch UnitDecode UnitDecode UnitExecute UnitExecute UnitPCIRControl Unitload R3,bload R4,cadd R3,R4store R3,a10111001001100…110111001010000…010100111001100…010111010001100…1load R4, c3050Operating Systems: A Modern Perspective, Chapter 4Slide 4-10Copyright © 2004 Pearson Education, Inc.Control Unit Operation• Fetch phase: Instruction retrieved from memory• Execute phase: ALU op, memory datareference, I/O, etc.PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) {execute(IR);PC = PC + sizeof(INSTRUCT);IR = memory[PC]; // fetch phase};Operating Systems: A Modern Perspective, Chapter 4Slide 4-11Copyright © 2004 Pearson Education, Inc.Primary Memory UnitMARMDRCommand012n-11234 98765Read Op:12341. Load MAR with addressread2. Load Command with “read”987653. Data will then appear in the MDROperating Systems: A Modern Perspective, Chapter 4Slide 4-12Copyright © 2004 Pearson Education, Inc.Processor Modes• Mode bit: Supervisor or User mode• Supervisor mode– Can execute all machine instructions– Can reference all memory locations• User mode– Can only execute a subset of instructions– Can only reference a subset of memory locationsOperating Systems: A Modern Perspective, Chapter 4Slide 4-13Copyright © 2004 Pearson Education, Inc.Kernels• The part of the OS critical to correct operation (trusted software)• Executes in supervisor mode•The trap instruction is used to switch from user to supervisor mode, entering the OSOperating Systems: A Modern Perspective, Chapter 4Slide 4-14Copyright © 2004 Pearson Education, Inc.Supervisor and User MemoryUserProcessUserProcessSupervisorProcessSupervisorProcessUserSpaceUserSpaceSupervisorSpaceSupervisorSpaceOperating Systems: A Modern Perspective, Chapter 4Slide 4-15Copyright © 2004 Pearson Education, Inc.Procedure Call and Message Passing Operating Systemscall(…);trapreturn;send(…, A, …);receive(…, B, …);receive(…A, …);…send(…, B, …);send/receiveOperating Systems: A Modern Perspective, Chapter 4Slide 4-16Copyright © 2004 Pearson Education, Inc.System Call Using the trap Instruction…fork();…fork() {…trap N_SYS_FORK()…}sys_fork()sys_fork() {/* system function */…return;}KernelTrap TableOperating Systems: A Modern Perspective, Chapter 4Slide 4-17Copyright © 2004 Pearson Education, Inc.A Thread Performing a System Call User Space Kernel Spacefork();sys_fork() {}ThreadOperating Systems: A Modern Perspective, Chapter 4Slide 4-18Copyright © 2004 Pearson Education, Inc.Examples of Exceptions in Pentium SystemsClass Cause Async/SyncReturn behaviorTrap Intentional exceptionSync always returns to next instructionFault Potentially recoverable errorSync might return to current instructionAbort nonrecover-able errorSync never returnsInterrupt signal from I/O deviceAsync always returns to next instructionOperating Systems: A Modern Perspective, Chapter 4Slide 4-19Copyright © 2004 Pearson Education, Inc.Examples of Exceptions• Kinds of Exceptions– traps, e.g. system calls– interrupts–faults– aborts• Pentium: Table of 256 different exception types– some assigned by CPU designers (divide by zero, memory access violations, page faults)– some assigned by