1The Impact of Wave-Pipelining on Future Interconnect TechnologyECE64682Wire Technology Issues•Low-k material integration•Decreases wire delay and power for on-chip interconnects•Wire sizing effects on resistivity•Impacts the delay of semi-global interconnects3Global Wire ConcernsDie area•Wire latency •Wire bit rate•Decoupled?Question #1: What impact do low-k materials have on bit rate?AB4Semi-Global Wire ConcernsDie area•Routed on higher density wiresQuestion #2: Can we overcome wiring sizing effects through design?•Latency critical wires• ITRS projects ρ increases5Outline•Introduction• Wave-Pipelining (WP) Concepts•Future Projection Assumptions•Global Interconnect WP Projections•Semi-Global Interconnect WP Projections•Conclusions6Traditional Wire PipelinesCLKPipeline RegisterABAB7Latency & Bit Rate TradeoffsCLKCLKCLKPRO’s CON’s•Bit rate increases•Overall latency increases•Power increases8Wave-Pipeline DefinitionCLKDataCLKRemove pipeline registers and let data propagate in “waves” along the wire90.0E+005.0E+081.0E+091.5E+092.0E+092.5E+093.0E+093.5E+094.0E+094.5E+095.0E+090 10 20 30 40 50Number of repeatersBits per secondThroughput Reciprocal Latency Supply voltage = 2 VInterconnect length = 1 cmR = 2672 ohm/cmC = 3.26 pf/cm L = 8.04e-10 H/cmRt = 180 ohm, Ct = 130 ff~4x Wave-Pipeline Bit-RateCLKCLK10Impact on Latency00.511.522.533.540 10 20 30 40 50Number of repeatersLatency (ns)Minimum latency = 1.58 nsLatency = 1.68 nsInterconnect length = 1 cmWidth of square cross-section = 250 nm Supply voltage = 2 VRepeater scaling factor = 56Only a ~6%  in latency!11Maximum Bit-Rate ComparisonTable I. Design of a 1cm interconnect circuit implemented in 180 nm technology Latch Insertion Wave pipelining Target Throughput 3 Gbps Number of latches/repeaters 20 18 Latency 3.33 ns 0.97 ns Total Power 6.23 mW 3.77 mW Wire Pitch 1.6 micron 1.6 micron Silicon Area 5.07e-5 cm2 1.05e-5 cm2 WP cuts latency by ~1/3WP cuts power by ~1/212Timing and Robustness?FIFO Re-TimerDataCLKFIFO Re-TimerDataFIFO Re-TimerDataFIFO Re-TimerDataFIFO Re-TimerDataFIFO Re-TimerDataFIFO Re-TimerDataFIFO Re-TimerDataSend clock lines with every 8 data lines!13Outline•Introduction•Wave-Pipelining (WP) Concepts• Future Projection Assumptions•Global Interconnect WP Projections•Semi-Global Interconnect WP Projections•Conclusions14Clock Frequency Projections1101001000100001000001980 1990 2000 2010 2020 2030YearLocal Clock Frequency(Mhz)1.4x increase every 3 years ~2x increase every 3 yearsITRS ProjectionsIntel Trends15Future Bit Rate ProjectionsMaximum throughput [6] Tmax=1σRCseglnK11 −ν1⎛⎝⎜⎞⎠⎟+ 0.693RtCt Sakurai time constant [12] 10.4RCseg t t t seg t seg seg segR C R C C R R Cσ σ= + + += Sakurai coefficient [12] 11.014t seg seg t seg segt seg seg t seg segR C R C R CR C R C R CKπ=+ ++ +⎡ ⎤⎢ ⎥⎢ ⎥⎢ ⎥⎣ ⎦ Voltage swing v1 calculated recursively [6] vn = 0.9 vn-1 = 1/(2- vn) Rt =Transistor equivalent output resistance Ct = Transistor equivalent input capacitance Rseg = Wire segment resistance Cseg = Wire segment capacitance n = number wire segments16Comparison to Simulation0.0E+002.0E+094.0E+096.0E+098.0E+091.0E+101.2E+100 10 20 30 40 50Number of repeaters per cmBitrate (bps)Reciprocal rise timeAnalytical throughput modelHSPICE simulations Bit Rate =1t90%,segReciprocal rise timeAnalytical bit rate modelHPSICE simulations17Comparison to SimulationVDD = 1.5 V0.0E+005.0E+081.0E+091.5E+092.0E+092.5E+093.0E+093.5E+094.0E+094.5E+090 10 20 30 40 50Number of repeaters per cmThroughput (bps)R = 2672 ohm/cmC = 3.26 pf/cm L = 0.804 nH/cmRt = 250 ohm, Ct = 130 ff18Comparison to Simulation VDD = 1 V0.0E+005.0E+081.0E+091.5E+092.0E+092.5E+093.0E+090 10 20 30 40 50Number of repeaters per cmThroughput (bps)R = 2672 ohm/cmC = 3.26 pf/cm L = 0.804 nH/cmRt = 420 ohm, Ct = 130 ff19Outline•Introduction•Wave-Pipelining (WP) Concepts•Future Projection Assumptions• Global Interconnect WP Projections•Semi-Global Interconnect WP Projections•Conclusions2002004006008001,0001,2001,400130nm 90nm 65nm 45nm 32nm 22nm(L=1cm)(L=1cm) (L=1cm)(L=1cm) (L=1cm)(L=1cm)Global Wire ProjectionsNo resistivity sizing effects!Aspect Ratio ~ 1.5Global Interconnect Pitch (nm)21Global ILD Options00.51.01.52.02.53.03.54.04.5180nm 130nm 90nm 65nm 45nm 32nm 22nmLow-k OptionConstant-k OptionRelative Dielectric Constant22Global Bit Rate Projections0246810121416180 130 90 65 45 32 22Technology Generation (nm)Target Bit Rate [Gbps]0123456789180 130 90 65 45 32 22Technology Generation (nm)Number of RepeatersDesign can meet bit rate targets with no ILD material changes!!Local fclk projectionsConstant-k option23Global Wire Delay00.511.522.53180 130 90 65 45 32 22Technology Generation (nm)Global Wire Time Delay Normalized to Clock PeriodPipelining is needed24Outline•Introduction•Wave-Pipelining (WP) Concepts•Future Projection Assumptions•Global Interconnect WP Projections• Semi-Global Interconnect WP Projections•Conclusions25Bypass Bus Example•180nm tech bypass bus in Itanium-2 (L=2mm)*•Bypass bus is needed to resolve data hazards•Bypass bus needs to have low latency to broadcast values to other F.U.’s•Directly impacts architectural performance*E.C. Fetzer, et al, “A Fully Bypassed Size-Issue Integer Datapath and Register File on the Itanium-2 Microprocessor,” IEEE J. Solid-State Circuits, 37 (11) Nov. 2002, pp.1433-1440.26Bypass Bus Scaling Example1/S Ideal Scaling (S=1.4)00.511.522.5180 130 90 65 45 32 22Technology Node (nm)Bypass Bus Length (mm)27Bypass Bus Pitch Projections1/S Ideal Scaling (S=1.4)0100200300400500600180 130 90 65 45 32 22Technology Node (nm)Semi-global Pitch Values(2.20 µΩ-cm)(2.20 µΩ-cm)(2.45 µΩ-cm)(2.57 µΩ-cm)(3.62 µΩ-cm)(4.14 µΩ-cm)(4.88µΩ-cm)28τ∝ RC =ρεILDL2λwire21s21s2tdelayIdeal Scaling⎯ →⎯⎯⎯tdelaySProblem … wire delay does not improve with ideal scalingBypass Bus Target Delay29Bypass Wire Delayconstant-klow-kconstant-klow-kNO repeatersWITH repeaters110180 130 90 65 45 32 22Technology Generation (nm)Wire Delay Normalized to Target Delay30Can we use wave-pipelining to help this situation?31Alternate Scaling Option?s0 s1 s2 s3 s4 s5 s6 s7s0s1s2s3s4s5s6s7Intermediate wire pitch2x intermediate wire pitch32Overhead CircuitsWave-Pipelined Multiplexed (WPM) RoutingDriverDriverReceiverReceiverRepeaters (Inverter pair)Repeaters (Inverter