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A Compiler-in-the-Loop (CIL) Framework to Explore Horizontally Partitioned Cache (HPC) Architectures

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A Compiler-in-the-Loop (CIL) Framework to Explore Horizontally Partitioned Cache (HPC) ArchitecturesPower in Embedded SystemsMemory SubsystemHorizontally Partitioned Cache (HPC)Performance Advantage of HPCPower Advantage of HPCsHPC Design ComplexityHPC Design Space ExplorationRelated WorkHPC Exploration FrameworkSlide 11ExperimentsImportance of HPC DSESlide 14Importance of Compiler-in-the-Loop DSESlide 16Design Space Exploration HeuristicsAchieved Energy ReductionExploration timeSummaryA Compiler-in-the-Loop (CIL) Framework A Compiler-in-the-Loop (CIL) Framework to Explore to Explore Horizontally Partitioned Cache (HPC) Horizontally Partitioned Cache (HPC) ArchitecturesArchitecturesAviral Shrivastava*, Ilya Issenin, Nikil Dutt*Compiler and Microarchitecture Lab,Center for Embedded Systems,Arizona State University, Tempe, AZ, USA.CCMMLLACES Lab,Center For Embedded Computer Systems,University of California, Irvine, CA, USACopyright © 2008 ASUASP-DAC 2008CCMMLL2Power in Embedded SystemsPower in Embedded SystemsPower: Most important factor in usability of electronic devicesPower: Most important factor in usability of electronic devicesDevice Battery life Charge timeBattery weight/ Device weightApple iPOD 2-3 hrs 4 hrs 3.2/4.8 ozPanasonic DVD-LX9 1.5-2.5 hrs 2 hrs 0.72/2.6 poundsNokia N80 20 mins 1-2 hrs 1.6/4.73 ozPerformance requirements of handheldsIncrease by 30X in a decadeBattery capacityIncrease by 3X in a decadeConsidering technological breakthroughs, e.g. fuel cellsCopyright © 2008 ASUASP-DAC 2008CCMMLLMemory SubsystemMemory SubsystemEmbedded System DesignEmbedded System DesignMinimize power at minimal performance lossMemory subsystem design parametersMemory subsystem design parametersSignificant impact on power and performanceMay be the major consumer of system powerMay be the major consumer of system powerVery significant impact on performanceVery significant impact on performanceNeed to be chosen very carefullyCompiler Compiler influences influences the way application uses the way application uses memorymemoryCompiler should take part in the design process3Compiler-in-the-Loop Memory DesignCopyright © 2008 ASUASP-DAC 2008CCMMLL4Horizontally Partitioned Cache Horizontally Partitioned Cache (HPC)(HPC)Originally proposed by Gonzalez et al. Originally proposed by Gonzalez et al. in 1995in 1995More than one cache at the same level More than one cache at the same level of memory hierarchyof memory hierarchyCaches share the interface to memory Caches share the interface to memory and processorand processorEach page is mapped to exactly one Each page is mapped to exactly one cachecacheMapping is done at page-level Mapping is done at page-level granularitygranularitySpecified as page attributes in MMUSpecified as page attributes in MMUMini Cache is relatively smallMini Cache is relatively smallExample: Intel StrongARM and XScaleExample: Intel StrongARM and XScaleProcessor PipelineMain CacheMini CacheMemoryCopyright © 2008 ASUASP-DAC 2008CCMMLL5Performance Advantage of HPCPerformance Advantage of HPCObservation: Often arrays have low Observation: Often arrays have low temporal localitytemporal localityImage copying: each value is used only once or a few timesBut the stream evicts all other data from the cacheSeparate low temporal locality data Separate low temporal locality data from high temporal locality datafrom high temporal locality dataArray a – low temporal locality – small (mini) cacheArray b – high temporal locality – regular (main) cachePerformance ImprovementPerformance ImprovementReduced miss rate of Array bTwo separate caches may be better than a unified cache of the total sizeProcessor Pipelinea[1000]b[5]Memorychar a[1024];char b[1024];for (int i=0; i<1024; i++) c += a[i]+b[i%5];Copyright © 2008 ASUASP-DAC 2008CCMMLL6Power Advantage of HPCsPower Advantage of HPCsPower savings due to two effectsPower savings due to two effectsReduction in miss rateAccessEnergy(mini cache) < AccessEnergy(main cache)Reduction in miss rateReduction in miss rateAligned with performanceExploited by performance improvement techniquesLess Energy per Access to mini cacheLess Energy per Access to mini cacheInverse to performanceEnergy can decrease even if there are more missesEnergy can decrease even if there are more missesOpposite to performance optimization techniquesCompiler (Data Partitioning) Techniques for Compiler (Data Partitioning) Techniques for performance improvement and power reduction performance improvement and power reduction are differentare differentCopyright © 2008 ASUASP-DAC 2008CCMMLL7HPC Design ComplexityHPC Design ComplexityPower reduction very sensitive on data partitionPower reduction very sensitive on data partitionUp to 2x difference in power consumptionPower reduction achieved is also very sensitive on Power reduction achieved is also very sensitive on the HPC design parameters, e.g., size, associativitythe HPC design parameters, e.g., size, associativityUp to 4x difference in power consumptionHPC DesignHPC ParametersChooseData PartitionApplicationData PartitionChooseHPC ParametersCopyright © 2008 ASUASP-DAC 2008CCMMLLJan 16, 2019Aviral Shrivastava Final Defense8HPC Design Space ExplorationHPC Design Space ExplorationTraditional ExplorationApplicationApplicationHPC ParametersCompilerExecutableCycle Accurate SimulatorCycle Accurate SimulatorSensitive CompilerExecutableCycle AccurateSimulatorCycle AccurateSimulatorCompiler-in-the-Loop ExplorationCompiler-in-the-Loop (CIL) Design Space Exploration (DSE)Compiler-in-the-Loop (CIL) Design Space Exploration (DSE)SynthesizeBest processor ConfigurationCopyright © 2008 ASUASP-DAC 2008CCMMLL9Related WorkRelated WorkHorizontally Partitioned CachesHorizontally Partitioned CachesIntel StrongARM SA 1100, Intel XScalePerformancePerformance-oriented data partitioning techniques for HPC-oriented data partitioning techniques for HPCNo Analysis (Region-based Partitioning)Separate array and stack variablesSeparate array and stack variablesGonzalez et al. [Gonzalez et al. [ICS’95ICS’95], Lee et al. [], Lee et al. [CASES’00CASES’00], Unsal et al. [], Unsal et al. [HPCA’02HPCA’02]]Dynamic Analysis (in hardware)Memory address; PC basedMemory address; PC basedJohnson et al. [Johnson et al. [ISCA’97ISCA’97], Rivers et al. [], Rivers


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