Fundamentals of Computer SystemsMemoryStephen A. EdwardsColumbia UniversitySpring 2012Atari Space Race, 1973Atari Space Race PCBFront Back (mirrored)Read-Only Memories: Combinational Functions2k× nROMA0A1A2...Ak−1D0D1...Dn−1General ROM:2kwordsn bits per word128 × 1ROMA0A1A2A3A4A5A6DExample:Space Race ROMcolumnrowImplementing ROMs0/10Z: “notconnected”010111Add. Data00 01101 11010 10011 0102-to-4DecoderA1A00 1 11 1 01 0 00 1 0Wordline 00Wordline 11Wordline 22Wordline 33Bitline 0D0Bitline 1D1Bitline 2D2Implementing ROMs0/10Z: “notconnected”010111Add. Data00 01101 11010 10011 0102-to-4Decoder1A10A00 1 11 1 01 0 00 1 0Wordline 00Wordline 11Wordline 22Wordline 33Bitline 0D0Bitline 1D1Bitline 2D210 00010Implementing ROMs0/10Z: “notconnected”010111Add. Data00 01101 11010 10011 0102-to-4DecoderA1A00123D0D1D2Implementing ROMs0/10Z: “notconnected”010111Add. Data00 01101 11010 10011 0102-to-4DecoderA1A00123D0D1D20 011101Atari Space Race SchematicThe 1971 DEC M792-YB Bootstrap Diode Matrix32-word, 16-bit (64-byte) ROM diode matrixCMOS Mask-Programmed ROMsAdd. Data00 01101 11010 10011 010ROM “programmed”by selectivelyconnecting drainwiresActive-highwordlinesMask ROM Die PhotoColor PROM in Pac-Man00 0001 0702 6603 EF04 0005 F806 EA07 6F08 0009 3F0A 000B C90C 380D A A0E AF0F F610 00......1F 00A Floating Gate MOSFETCross section of a NOR FLASH transistor. Kawai et al., ISSCC 2008 (Renesas)Floating Gate n-channel MOSFETChannelDrainSourceFloating GateControl GateSiO2Floating gate uncharged; Control gate at 0V: OffFloating Gate n-channel MOSFETChannelDrainSourceFloating GateControl GateSiO2+++++++++− − − − − − −−+++++++++− − − − − − −−Floating gate uncharged; Control gate positive: OnFloating Gate n-channel MOSFETChannelDrainSourceFloating GateControl GateSiO2− − −−− − −−++++++++Floating gate negative; Control gate at 0V: OffFloating Gate n-channel MOSFETChannelDrainSourceFloating GateControl GateSiO2++++++++− − − − − − −−−++Floating gate negative; Control gate positive: OffEPROMs and FLASH use Floating-Gate MOSFETsStatic Random-Access Memory CellWord lineBit line Bit lineLayout of a 6T SRAM Cell ! !$% $%&$'() "#Weste and Harris. Introduction to CMOS VLSI Design.Addison-Wesley, 2010.Intel’s 2102 SRAM, 1024 × 1 bit, 19722102 Block DiagramSRAM TimingA12A11A2A1A0CS2D7D6D1D0......CS1WEOE62648K × 8SRAMCS1CS2WEOEAddr1 2Datawrite 1 read 26264 SRAM Block DiagramCY6264-1A1A2A3A4A5A6A7A8I/O0256 x 32 x 8ARRAYINPUT BUFFERCOLUMN DECODERPOWERDOWNI/O1I/O2I/O3I/O4I/O5I/O6I/O7CE1CE2WEOEGalaga CPU detail (Namco/Midway 1981)Dynamic RAM CellWord lineBit lineOur Old Pal, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D7meansandmeansOur Old Pal, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D7The decoder or“AND plane”In a RAM or ROM,computes everymintermPattern is notprogrammableOur Old Pal, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D7The decoder or“OR plane”One term for everyoutputPattern isprogrammable =the contents of theROMOur Old Pal, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D7Can we do better?Simplifying the Space Race ROM0 0 0 00 0 0 00 1 0 00 0 0 0A0A1A2A30 0 0 00 0 0 01 1 0 00 0 0 00 0 0 00 0 0 00 1 0 00 0 1 00 0 0 01 0 0 00 1 1 10 0 0 10 0 1 01 0 0 00 0 1 00 1 0 00 0 0 11 1 1 10 1 1 11 0 0 00 1 0 00 0 0 00 1 0 00 0 0 01 0 0 00 0 0 00 1 0 00 0 0 0Essential mintermsmean don’t expand theseOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D73210D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D73210321D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210321 03103210D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210321 031032103 21032 10D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210321 031032103 21032 10310202132 1 0D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210321 031032103 21032 10310202132 1 03 2 10D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsOur New PAL, the Space Race ROM0123456789101112131415A0A1A2A3D0D1D2D3D4D5D6D732103213210321 031032103 21032 10310202132 1 03 2 103 2 1 0D0= 3210D1= 321D2= 3210 + 3210D3= 321 0 + 310+3210 + 3210D4= 3 210 + 321 0+32 10 + 3210D5= 310 + 20 + 21+321 0 + 32 1 0D6= 3 2 10 + 3210D7= 3 2 1 0 + 3210Saved two ANDsA 22V10 PAL: Programmable AND/Fixed OR0 4 8 1216202428IncrementsFirstFuseNumbers32 36 40Macro-cellR = 5809P = 5808R = 5811P = 5810R = 5813P = 5812R = 5815P = 5814R = 5817P = 5816Asynchronous Reset232221201912345(to all registers)396044088092414521496211221562860I/O/QI/O/QI/O/QI/O/QI/O/QIIIICLK/IMacro-cellMacro-cellMacro-cellMacro-cellField-Programmable Gate Arrays (FPGAs)Switch BlockLE LE LESB SBLE LE LELUT16×1 RAMprogrammable switchSwitch Box: