Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Lens Aberration Aware Timing-Driven PlacementAndrew B. Kahng†‡*Chul-Hong Park‡Puneet Sharma‡Qinke Wang†CSE† and ECE‡ Departments, UC San Diego*Blaze DFM, Inc., Sunnyvale, CA2OutlineLens Aberration and BackgroundPlacement Formulation and SolverAberration-Aware Timing FlowExperimentsSummary3Lithography SystemLithography tool images a complex chip pattern with billions of pixels on waferFull-wafer exposure  Step-and-repeat  Step-and-scan systemProduce multiple copies of chips with one mask Illumination SourceCondenser LensProjection LensLens SlitMaskWaferLens4Lens AberrationLens Aberrations: image distortion induced by imperfect lens systemOptical path differences among light rays  wavefront deviation from reference sphere at the exit pupil  blur and distortion of images Variety of effects on lithographic imaging shifts in image position, image asymmetry, reduction of process windowImage planeIlluminationray5Zernike Aberration CoefficientsZernike Coefficients represent wavefront aberrations36 Zernike termsComa  image asymmetry, pattern-dependent image shiftAstigmatism  CD difference between horizontal, vertical linesSpherical  changes best DOF between dense/isolated patternsComaAstigmatismSpherical6Zernike Coefficients with lens fieldSlit scans from one side of the field to anotherZernike coefficients vary with position in the lens field  CD also varies along horizontal direction  CD stays constant along vertical direction Astigmatism variation  pushes designer toward single-directional layoutsGate CDs of each master cell change according to lens positionDevice performances vary across the chips in a lens fieldAstigmatismX-comaY-comaSphericalLens PositiondifferentReticle (mask) mapsame7An Example: Coma AberrationComa Aberration  path difference in the horizontal direction  CD asymmetry between left and right devices in pattern shownCD variation: -15nm to 20nm in early 193nm scanners  CD skews between devices increase circuit delay8Impact on Gate CDImpact on average cell delay varies with location in lens field  Average CD 93nm – 97nm for NAND2X4Different devices in a cell affected differentlyCD skew: Max difference in CD of devices in a cell  CD Skew up to 5nm for NAND2X49Impact on Gate DelayImpact on average cell delay varies with location in lens field  NAND2X4 delay varies between -2% and 2%Delay skew: Max difference over all timing arc delays  NAND2X4 has delay skew increase of up to 60%Input capacitance and slews increase with CDPredictable “fast” and “slow” regions due to aberrationPlace setup-critical cells in the fast regions, and place hold-critical cells in the slow regions10OutlineLens Aberration and BackgroundPlacement Formulation and SolverAberration-Aware Timing FlowExperimentsSummary11Placer: APlaceGlobal Placement (NP-hard) as a Constrained Nonlinear Optimization Problem: We divide the placement area into uniform bins, and seek to minimize total half-perimeter wirelength (HPWL) under the constraint that total cell area in every bin is equalized.min HPWL (x,y) s.t. Dg (x,y) = D for each global bin gDg (x,y) : density function that corresponds to the total cell area in a given global bin “g”D : average cell area over all global bins12Non-Linear OptimizationApply smooth approximation of placement objectives: wirelength, density function, etc.Quadratic Penalty methodSolve sequence of unconstrained minimization problems for sequence of µ  0Conjugate Gradient solverFind unconstrained minimum of a high-dimensional functionMemory required is only linear in problem size  adaptable to large-scale placement problems13High Quality and ExtensibilityIBM ISPD'05 Placement ContestTestcases directly derived from industrial ASIC designs, preserve physical structure of designLarge amounts of whitespace, fixed blocks and (peripheral or area) I/Os, up to 2.1 million componentsAPlace2.0 was contest winnerStrong ExtensibilityWirelength-Driven Mixed-Size Placement [ISPD04, ICCAD04, TCAD05, ISPD05, ICCAD05]Timing Driven Placement [ICCAD04]Power Aware Placement [DAC05]Voltage Drop Aware Placement [ICCD05]Aberration-Aware Placement [DATE06]14Aberr-Aware Placement FormulationGoal: Minimize total timing-weighted delays of timing-critical cells and total timing-weighted net wirelengthWWL is sum of timing-weighted net HPWL valuesWa is weight of the aberration-aware timing-driven objectivegtv(xv) is delay function for cell v’s model tvIf there are multiple (n>1) chips, gitv(xv) is delay function for ith chipWe consider the maximum delay of cell v over all copies  improve performance of slowest chips (with pessimism)15Weight Function: timing-criticality exponentµ: expected improvement of the longest (or shortest) delayTs = (1-µ)maxπ{delay(π)} for setup-critical path Th = (1+µ)minπ{delay(π)} for hold-critical path slacks(π) = Ts -delay(π): slack of a setup-critical path π slackh(π) = delay(π)-Th: slack of a hold-critical path πwhereAssign timing weights to cells based on timing criticality and path sharing  Cell on a timing critical path receives a heavy weightCompute a weight for each timing-critical pathObtain the timing weight of a cell by summing up the weights of timing critical paths16Smoothing of Delay VariationsPurpose of smoothingDelay functions have accurate values only at discrete locationsUse linear interpolation to get cell delays at continuous positions in lens field  can compute gradientsSmoothing factor β17OutlineLens Aberration and BackgroundPlacement Formulation and SolverAberration-Aware Timing FlowExperimentsSummary18Standard Timing Analysis FlowStandard Cell GDSSPICE NetlistLibraryCharacterizationSPICE ModelDelay ExtractionProblem: With aberration, two instances of the same master should have different timing models !19Aberration-Aware Timing FlowStandard Cell GDSPrint ImageGDSLens PositionSRAF GenerationOPCLithography SimulationCD MeasurementSPICE NetlistLibraryCharacterizationTransistor-levelTiming Library (TTL)Delay LUTsLVSSPICE ModelTwo main stepsConstruct litho models  get