Lens Aberration (32 pages)

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Lens Aberration



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Lens Aberration Aware Timing Driven Placement Andrew B Kahng Chul Hong Park Puneet Sharma Qinke Wang CSE and ECE Departments UC San Diego Blaze DFM Inc Sunnyvale CA Outline Lens Aberration and Background Placement Formulation and Solver Aberration Aware Timing Flow Experiments Summary 2 Lithography System Illumination Source Lens Slit Lens Condenser Lens Mask Projection Lens Wafer Lithography tool images a complex chip pattern with billions of pixels on wafer Full wafer exposure Step and repeat Step and scan system Produce multiple copies of chips with one mask 3 Lens Aberration Image plane Illumination ray 4 Lens Aberrations image distortion induced by imperfect lens system Optical path differences among light rays wavefront deviation from reference sphere at the exit pupil blur and distortion of images Variety of effects on lithographic imaging shifts in image position image asymmetry reduction of process window Zernike Aberration Coefficients Spherical Coma Astigmatism 5 Zernike Coefficients represent wavefront aberrations 36 Zernike terms Coma image asymmetry pattern dependent image shift Astigmatism CD difference between horizontal vertical lines Spherical changes best DOF between dense isolated patterns Zernike Coefficients with lens field Slit scans from one side of the field to another Zernike coefficients vary with position in the lens field CD also varies along horizontal direction CD stays constant along vertical direction Astigmatism variation pushes designer toward single directional layouts X coma Astigmatism Spherical Y coma Lens Position different Gate CDs of each master cell change according to lens position Device performances vary across the chips in a lens field 6 same Reticle mask map An Example Coma Aberration Coma Aberration path difference in the horizontal direction between left and right devices in pattern shown CD variation 15nm to 20nm in early 193nm scanners CD skews between devices increase circuit delay 7 CD asymmetry Impact on Gate CD Impact on average cell delay varies with location in lens field Average CD 93nm 97nm for NAND2X4 Different devices in a cell affected differently CD skew Max difference in CD of devices in a cell CD Skew up to 5nm for NAND2X4 8 Impact on Gate Delay Impact on average cell delay varies with location in lens field NAND2X4 delay varies between 2 and 2 Delay skew Max difference over all timing arc delays NAND2X4 has delay skew increase of up to 60 Input capacitance and slews increase with CD 9 Predictable fast and slow regions due to aberration Place setup critical cells in the fast regions and place hold critical cells in the slow regions Outline Lens Aberration and Background Placement Formulation and Solver Aberration Aware Timing Flow Experiments Summary 10 Placer APlace Global Placement NP hard as a Constrained Nonlinear Optimization Problem We divide the placement area into uniform bins and seek to minimize total half perimeter wirelength HPWL under the constraint that total cell area in every bin is equalized min HPWL x y s t Dg x y D for each global bin g Dg x y density function that corresponds to the total cell area in a given global bin g D average cell area over all global bins 11 Non Linear Optimization Apply smooth approximation of placement objectives wirelength density function etc Quadratic Penalty method Solve sequence of unconstrained minimization problems for sequence of 0 Conjugate Gradient solver Find unconstrained minimum of a high dimensional function Memory required is only linear in problem size adaptable to large scale placement problems 12 High Quality and Extensibility IBM ISPD 05 Placement Contest Testcases directly derived from industrial ASIC designs preserve physical structure of design Large amounts of whitespace fixed blocks and peripheral or area I Os up to 2 1 million components APlace2 0 was contest winner Strong Extensibility Wirelength Driven Mixed Size Placement ISPD04 ICCAD04 TCAD05 ISPD05 ICCAD05 Timing Driven Placement ICCAD04 Power Aware Placement DAC05 Voltage Drop Aware Placement ICCD05 Aberration Aware Placement DATE06 13 Aberr Aware Placement Formulation Goal Minimize total timing weighted delays of timingcritical cells and total timing weighted net wirelength WWL is sum of timing weighted net HPWL values W a is weight of the aberration aware timing driven objective gtv xv is delay function for cell v s model tv If there are multiple n 1 chips g itv xv is delay function for ith chip We consider the maximum delay of cell v over all copies improve performance of slowest chips with pessimism 14 Weight Function Assign timing weights to cells based on timing criticality and path sharing Cell on a timing critical path receives a heavy weight where timing criticality exponent expected improvement of the longest or shortest delay Ts 1 max delay for setup critical path Th 1 min delay for hold critical path slacks Ts delay slack of a setup critical path slackh delay Th slack of a hold critical path 15 Compute a weight for each timing critical path Obtain the timing weight of a cell by summing up the weights of timing critical paths Smoothing of Delay Variations Purpose of smoothing Delay functions have accurate values only at discrete locations Use linear interpolation to get cell delays at continuous positions in lens field can compute gradients Smoothing factor 16 Outline Lens Aberration and Background Placement Formulation and Solver Aberration Aware Timing Flow Experiments Summary 17 Standard Timing Analysis Flow Standard Cell GDS SPICE Netlist Library Characterization SPICE Model Delay Extraction Problem With aberration two instances of the same master should have different timing models 18 Aberration Aware Timing Flow Standard Cell GDS SRAF Generation OPC Lens Position Lithography Simulation Print Image GDS Delay LUTs Transistor level Timing Library TTL Library Characterization SPICE Netlist CD CD Measurement Measurement Two main steps Construct litho models get simulated gate CDs of each instance Generate timing library models of all masters for different locations 19 SPICE Model LVS OPC GDSII Generation SRAF Sub Resolution Assist Cell Bar GDS Feature or Standard Scattering Delay LUTs Extremely narrow lines do not print on wafer SRAF Generation Enhance process window Transistor level Timing Library TTL OPC Optical Proximity Correction OPC to match Layout modification Library photo resist edges to layout edgeCharacterization limited ability to compensate for Lens Lithography


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