IA32 Paging SchemeWhat is ‘paging’?What’s ‘paging’ good for?Why use ‘paging’?Several ‘paging’ schemesTerminologyControl Register CR3Page-DirectoryTwo-Level Translation SchemeAddress-translationPage-Level ‘protection’Format of a Page-Table entryFormat of a Page-Directory entryViolationsThe Error-Code formatControl Register CR2Slide 17Our ‘ioremap.c’ demoSlide 19‘ioread32()’In-class exercise #1In-class exercise #2IA32 Paging SchemeIntroduction to the Intel x86’s support for “virtual” memoryWhat is ‘paging’?•It’s a scheme for dynamically remapping addresses for fixed-size memory-blocks Virtual address-spacePhysical address-spaceWhat’s ‘paging’ good for?•For efficient ‘time-sharing’ among multiple tasks, an operating system needs to have several programs residing in main memory at the same time •To accomplish this using actual physical memory-addressing would require doing address-relocation calculations each time a program was loaded (to avoid conflicting with any addresses already being used)Why use ‘paging’? •Use of ‘paging’ allows ‘relocations’ to be done just once (by the linker), and every program can ‘reuse’ the same addresses Task #1Task #2Task #3 physical memorySeveral ‘paging’ schemes•Intel’s design for ‘paging’ has continued to evolve since its introduction in 80386 CPU•New processors support the initial design, as well as several optional extensions•We shall describe the initial design which is simplest and remains as the ‘default’ •It is based on subdividing the entire 4GB virtual address-space into 4KB blocksTerminology•The 4KB memory-blocks are called ‘page frames’ -- and they are non-overlapping•Therefore each page-frame begins at a memory-address which is a multiple of 4K•Remember: 4K = 4 x 1024 = 4096 = 212•So the address of any page-frame will have its lowest 12-bits equal to zeros•Example: page six begins at 0x00006000Control Register CR3•Register CR3 is used by the CPU to find the tables in memory which will define the address-translation that it should employ •This table is called the ‘Page Directory’ and its address must be ‘page-aligned’Physical Address of the Page-Directory31 0Page-Directory•The Page-Directory occupies one frame, so it has room for 1024 4-byte entries•Each page-directory entry may contain a pointer to a further data-structure, called a Page-Table (also page-aligned 4KB size)•Each Page-Table occupies one frame and has enough room for 1024 4-byte entries•Page-Table entries may contain pointersTwo-Level Translation Scheme PAGEDIRECTORYCR3 PAGETABLES PAGEFRAMESAddress-translation•The CPU examines any virtual address it encounters, subdividing it into three fields offset into page-frame index intopage-directory index into page-table31 22 21 12 11 0 10-bits 10-bits 12-bits This field selects one of the 1024 array-entries inthe Page-Directory This field selects one of the 1024 array-entries in that Page-Table This field provides the offset to one of the 4096 bytes in that Page-FramePage-Level ‘protection’•Each entry in a Page-Table can assign a collection of ‘attributes’ to the Page-Frame that it points to; for example:–The P-bit (page is ‘present’) can be used by the operating system to support its implementation of “demand paging”–The W/R-bit can be used to mark a page as ‘Writable’ or as ‘Read-Only’ –The U/S-bit can be used to mark a page as ‘User accessible’ or as ‘Supervisor-Only’Format of a Page-Table entryPAGE-FRAME BASE ADDRESS PWUPWTPCDAD0031 12 11 10 9 8 7 6 5 4 3 2 1 0AVAILLEGEND P = Present (1=yes, 0=no) W = Writable (1 = yes, 0 = no) U = User (1 = yes, 0 = no) A = Accessed (1 = yes, 0 = no) D = Dirty (1 = yes, 0 = no)PWT = Page Write-Through (1=yes, 0 = no)PCD = Page Cache-Disable (1 = yes, 0 = no)Format of a Page-Directory entryPAGE-TABLE BASE ADDRESS PWUPWTPCDA0PS031 12 11 10 9 8 7 6 5 4 3 2 1 0AVAILLEGEND P = Present (1=yes, 0=no) W = Writable (1 = yes, 0 = no) U = User (1 = yes, 0 = no) A = Accessed (1 = yes, 0 = no)PWT = Page Write-Through (1=yes, 0 = no)PCD = Page Cache-Disable (1 = yes, 0 = no)PS = Page-Size (0=4KB, 1 = 4MB)Violations•When a task violates the page-attributes of any Page-Frame, the CPU will generate a ‘Page-Fault’ Exception (interrupt 0x0E)•Then the operating system’s page-fault exception-handler gets control and can take whatever action it deems is suitable•The CPU will provide help to the OS in determining why a Page-Fault occurredThe Error-Code format•The CPU will push an Error-Code onto the operating system’s stackPW/RU/ Sreserved (=0) 3 2 1 0Legend: P (Present): 1=attempted to access a ‘not-present’ page W/R (Write/Read): 1=attempted to write to a ‘read-only’ page U/S (User/Supervisor): 1=user attempted to access a ‘supervisor’ page ‘User’ means that CPL = 3; ‘Supervisor’ means that CPL = 0, 1, or 2Control Register CR2•Whenever a ‘Page-Fault’ is encountered, the CPU will save the virtual-address that caused that fault into the CR2 register–If the CPU was trying to modify the value of an operand in a ‘read-only’ page, then that operand’s virtual address is written into CR2–If the CPU was trying to read the value of an operand in a supervisor-only page (or was trying to fetch-and-execute an instruction) while CPL=3, the relevant virtual address will be written into CR2‘ioremap()’ and ‘iounmap()’•The Linux kernel offers ‘helper functions’ that let modules request modifications to the kernel’s page-mapping tables•Examples: void * ioremap( phys_addr, length );adds page-table entries that ‘map’ the regionvoid iounmap( void *virt_addr );remove previously created page-table entriesOur ‘ioremap.c’ demo•To illustrate use of the ‘ioremap()’ function we created this Linux kernel module•It asks the kernel to set up a ‘mapping’ of the page at physical address 0xFEE00000 into the kernel’s virtual address-space•This is the page where each processor’s Local-APIC resides •Each APIC register is ‘paragraph-aligned’Multi-CORE CPUMultiple Logical Processors CPU0CPU1I/OAPICLOCALAPICLOCALAPICEach processor’s Local-APIC contains a 32-bit register (at offset 0x20) known as the Local-APIC Identification Register which has an 8-bit