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GVSU EGR 214 - Digital Logic

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EGR214 Laboratory Activities 1School of EngineeringGrand Valley State UniversityEGR 214 – Laboratory #10Digital LogicObjectives• To experiment with digital logic concepts and componentsPre-Lab Assignment1. Read through the entir e laboratory procedure.Pre-Lab DeliverablesThese deliverables are due at the beginning of your laboratory period. Your instructor will verifythese deliverables as you enter the labor atory and will use them to construct your lab oratory grade.1. None for this lab.Part I – A Digital InverterIn EGR226 we introduce you to digital signals, which are signals tha t convey information but only take onone o f two values rather than a continuum of values. The circuit of Figure 1 can be thought of as a “digitalinverter”, one that takes a digital signal and cons tructs its opposite. In this par t of the lab oratory we willwork with signals tha t are o nly 0V (representing “logic low”) and 9V (representing “logic high”). It’s OK ifthe voltages aren’t exact – anything less tha n 1V can reas onably be considered “low” and anything greaterthan 8V can reasonably be considered “high”.Although most digital devices use 0V and 5V to represent logic low and logic high re spectively, the uppervoltage is arbitrary and indeed many modern devices consider 3.3V to be logic high, or 1.8V, or other values.The key behind digital signals is that there are only two expected voltage values, a high one and a low one.+9V10kΩ10kΩ1kΩvin2N7000voutFigure 1: Digital inverter circuitCopyrightc 2010 Padnos College of Engineering & ComputingEGR214 Laboratory Activities 21. Construct the circuit o f Figure 1. Recall the pinout of the 2N7000 MOSFET:Also remember that MOSFET’s are highly static-sensitive and you should ground yourself often andtouch the MOSFET pins as little as possible. In fact, the 10kΩ resistor from gate-to-so urce is intendedto drain away any charge that might accumulate at the gate thus prevents the MOSFET fro m beingdamaged. In the absence of any driving voltage at the vinnode, this gate-to-source resistor serves to“pull down” the voltage at the gate to be 0V. Unsurprisingly, a resistor used in this way is often calleda pull-down resistor.2. Power on the circ uit and complete the following table (the voutcolumn):vinvout0V9VShow your results to your instructo r.• Explain in your report how this circuit acts as a “digital inverter ”. Why are the voltages as they are(use circuit laws to explain)?3. Consider the circ uit of Figure 1 with the input vin= 0 V as shown in Figure 2 (or you can leave theinput vindisconnected since the 10kΩ pull-down res istor serves to keep the MOSFET off). Even withthe MOSFET off, some drain-to-source leakag e current Idsswill flow. The 2N7000 datasheet guaranteesthat Idss≤ 1µA at room temperatur e . This leakage current varies strongly with temperature suchthat Idss≤ 1mA at 1 25oC, or 1000 times as much as at room temperature.+9V10kΩ1kΩ2N7000voutIdssR = 10kΩFigure 2: A MOSFET allows some drain-to -source leakage current Idssto flow even when it is co mpletelyoff.Complete the following table assuming:Copyrightc 2010 Padnos College of Engineering & ComputingEGR214 Laboratory Activities 3• The MOSFET is off• Idss= 1µA (room temperature)• The upper 10kΩ resistor (from +9V to MO SFET dra in) varies as shown in the tableR vout(V)100Ω1kΩ10kΩ100kΩ1MΩ10MΩ• Include the co mpleted table in your report.• Explain in your report why the drain resisto r in the inverter circuit of Figure 1 cannot be “too large”.4. Consider the circuit of Figure 1 with the input vin= 9V as shown in Figure 3. With the MOSFETon, the drain-to-source current Idis limited by the construction of the MO SFET. The 2N7000 requiresthat Id≤ 200mA at room temperature, and even this limit is an absolute maximum which should not,in practice, be sustained for any length of time. At elevated ambient temperatures, this maximumdrain-to-source current should be even lower else the 2N7000 will be damaged due to overheating.+9V10kΩ1kΩ2N7000voutR = 10kΩ+9VIdFigure 3: A MOSFET is limited in how much drain-to-source current Idit can carry when it is on.Even if we are n’t worried about damaging the MOSFET, the current Idis “wasted” as it doesn’t doany useful work other than flowing through the uppe r resistor R thus causing voutto be near 0V. Weshould aim to waste as little cur rent as possible.Complete the following table assuming:• The MOSFET is on and its on-resistance is negligible (it’s about 5Ω for a 2N70 00)• The upper 10kΩ resistor (from +9V to MO SFET dra in) varies as shown in the tableR Id(mA)100Ω1kΩ10kΩ100kΩ1MΩ10MΩCopyrightc 2010 Padnos College of Engineering & ComputingEGR214 Laboratory Activities 4• Include the co mpleted table in your report.• Explain in your report why the drain resistor in the inverter circuit of Figure 1 c annot be “too small”.Part II – A Digital Memory Storage ElementThe digital inverter circuit of Figure 1 has an output that is a function of the present input, rega rdless ofwhat the input was in the past. This is an example of a circuit with no memory. However, we can construct acircuit that “remembers where it’s been”, and has an o utput voltage that not only depends upo n the presentinput, but also on the previous output(s). This type of circuit is said to have memory, and the principle of“circuits with memory” is at the core of today’s digital cir c uits.One such circuit-with-memory is called a set-reset latch, or S-R latch for short. It can be constructedfrom MOSFET’s or op-amps, but doing so takes a fair amount of thought and design. For the curious (andmotivated) an op-amp implementation of an S-R latch is shown in Figure 4.-+vout+--+VTRfRiRiv1+9V+9VR1R2TLV2372+-VTRfRiRiTLV2372v2Figure 4: Op-amp implementation of a set-reset la tchAn S-R latch behaves like a light switch on a wall. When you push up on the switch, the light turnson and stays on – you don’t have to keep pushing up. No matter how many more times you push up onthe switch, the light doesn’t turn any “more on”. Similarly, when you push down on the light switch, thelight turns off and stays off. Thus, this light switch has memory. In the circuit of Figure 4 for example, thefollowing behavior occurs:• When v1= 9V and v2= 0V then the output voutbec omes 9V. We call this the “set” state and isanalogous to “pushing up on the


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