COE/EE 243Digital LogicSession 23; Page 1/2Spring 2003COE/EE 243Homework Assignment #6Due Tuesday March 25 by 2:00pmShow your work on all of the problems below. If you want to see sample problems with solutions go tohttp://web.ddpp.com/student/student.html or the examples on the course web page.1. Realize the following functions using a PLA (try to optimize use of the PLA):XABDA¼C¼BCC¼D¼YA¼C¼ADC¼D¼ZCDA¼C¼ADAB¼DProvide the PLA table and sketch the equivalent circuit. How many gates and gate inputs areneeded?2. Repeat problem 1 using the PAL shown on the next page. Fill in the appropriate connections.How many gates and gate inputs are needed. Does this differ from the number required with thePLA? Explain.3. Design a full adder module with data input X and Y, carry input Cin, Sum output S, and Carryoutput Coutusing:(a) A 3-8 decoder and NAND gates(b) 4-to-1 multiplexers4. Problem 5.28 in your text5. Design a BCD adder that adds two BCD digits and produces a BCD result and a carry output andindicates an overflow.COE/EE 243Digital LogicSession 23; Page 2/2Spring 2003PAL