INTRODUCTIONIP coresNeed for IP coresIntellectual Property CategoriesCommercially Available Cryptographic IP core Vendors (by AlgIP Core Comparison ParametersIP Core Comparison charts for different cryptographic algoriBest of class IP coresCryptographic ChipsNeed for Cryptographic chipsCommercially Available Cryptographic Chip ManufacturersCryptographic Chip Comparison ParametersComplete list of Commercially Available Cryptographic Chips Best of class comparison for Cryptographic ChipsConclusion1Survey of commercially available cryptographic chips and IP cores implementing cryptographic algorithms (December 2005)P. Arora, M. Dugan, P. Gogte, GMU Abstract— The objective for this project is to analyze the cryptographic chips and IP cores that are commercially available today. This analysis includes a market survey and seeks out any published datasheets and implementations for these chips. From the published data, the project analysis includes a review of the advertised parameters and establishes evaluation criteria upon which a product comparison can be made. This project attempts to offer a “best of class” product based on the evaluation criteria. Index Terms—IP core, Cryptographic Chip, TPM, Security cores, Security Chip. I. INTRODUCTION Due to an increasing demand for system security, a large computational burden is being placed on computing resources to perform cryptographic operations. To prevent these operations from affecting the overall system performance, a new breed of chips has emerged that handles all cryptographic and system security requirements. Although these new chips offer greater flexibility when designing a system, computer designers need to carefully consider the parameters of each product to ensure that all security needs are met. The objective for this project is to analyze the cryptographic chips and IP cores that are commercially available today. This analysis includes a market survey and seeks out any published datasheets and implementations for these chips. From the published data, the project analysis includes a review of the advertised parameters and establishes evaluation criteria upon which a product comparison can be made. This project attempts to offer a “best of class” product based on the evaluation criteria II. IP CORES An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. Manuscript received Dec 19, 2005. P. Arora, and. Gogte are electrical engineering students at George Mason University under the supervision of Dr. Gaj ([email protected], [email protected]) M. Dugan is a computer engineering student at George Mason University under the supervision of Dr. Gaj. ([email protected]) IP cores are a major part of the electronic design automation (EDA) industry trend which repeatedly uses previously designed components. An IP core is a design function with well-defined interfaces. Many IP cores can be considered as a block of design for a specific chip that handles a specific functionality, and then evolves to a standard block of functionality, which can be used in multiple chips. An IP core should be entirely portable i.e.: it can be easily used in any vendor technology or design. The difference between a block on a single design (chip) and an IP core is that the signaling protocol and the clock definition can be significantly different between chips. An IP core needs to be flexible enough to handle these differences. Some examples of IP cores are Universal Asynchronous Receiver/Transmitter (UART), central processing units (CPUs), Ethernet controllers, and PCI interfaces. III. NEED FOR IP CORES In today’s rapidly growing chip technology, the number of gates per chip can reach several millions. To overcome the design gap generated by such fast-growing capacity and lack of available manpower, reuse of the existing designs becomes a very important concept in design methodology. IC designers typically use pre designed modules to avoid redesigning the entire logic for every new product. Utilizing the pre designed modules accelerates the development of new products to meet today’s time-to-market challenges. By practicing design-reuse techniques ie: by using blocks that have already been designed, and verified, various blocks of a large ASIC/SOC can be assembled quite rapidly. Another advantage of reusing the existing blocks is to reduce the possibility of failure based on design and verification of a block for the first time. These pre designed modules are commonly called Intellectual Property (IP) cores. IV. INTELLECTUAL PROPERTY CATEGORIES To provide various levels of flexibility for reuse and optimization, IP cores are classified into three different categories: hard cores, soft cores and firm cores.2 Hard IP cores: Hard cores are physical manifestations of the IP design. They consist of hard layouts using particular physical design libraries and are delivered in masked-level designed blocks (GDSII format- a stream format that represents hexadecimal description in variable length records to describe graphical data). These cores offer optimized implementation and the highest performance for their chosen physical library. The integration of hard IP cores is simple and the core can be dropped into an SOC physical design with very little effort. However, hard cores are technology dependent and provide minimum flexibility and portability in reconfiguration and integration across multiple designs and technologies. They are best for plug-and-play applications. Soft IP cores: They are delivered as RTL (Register transfer level) VHDL code to provide functional descriptions of IP cores. These cores offer maximum flexibility and re configurability to match the requirements of a specific design application, however they must be synthesized, optimized, and verified by their user before integration into designs. Being synthesizable, soft IP cores are compatible with the ASIC design flow. The SoC design can therefore be optimized for a specific silicon process and performance target. Therefore, the quality of a soft IP is highly dependent on the effort needed in the IP integration stage of SOC design. Firm IP cores: These cores are a combination of advantages of both hard cores and soft cores and balance the high performance and optimization properties of hard IP cores with the flexibility of soft IP
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