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About This PresentationA Few Words About Where We Are HeadedII Instruction Set Architecture5 Instructions and Addressing5.1 Abstract View of HardwareData TypesRegister ConventionsRegisters Used in This Chapter5.2 Instruction FormatsAdd, Subtract, and Specification of ConstantsMiniMIPS Instruction Formats5.3 Simple Arithmetic/Logic InstructionsArithmetic/Logic with One Immediate Operand5.4 Load and Store Instructionslw, sw, and lui InstructionsInitializing a Register5.5 Jump and Branch InstructionsConditional Branch InstructionsComparison Instructions for Conditional BranchingExamples for Conditional BranchingCompiling if-then-else Statements5.6 Addressing ModesFinding the Maximum Value in a List of IntegersThe 20 MiniMIPS Instructions Covered So Far6 Procedures and Data6.1 Simple Procedure CallsIllustrating a Procedure CallRecalling Register ConventionsA Simple MiniMIPS ProcedureNested Procedure Calls6.2 Using the Stack for Data StorageMemory Map in MiniMIPS6.3 Parameters and ResultsExample of Using the Stack6.4 Data TypesASCII CharactersLoading and Storing BytesMeaning of a Word in Memory6.5 Arrays and PointersSelection SortSelection Sort Using the Procedure max6.6 Additional InstructionsLogical ShiftsUnsigned Arithmetic and Miscellaneous InstructionsThe 20 MiniMIPS Instructions from Chapter 6 (40 in all so far)Table 6.2 The 37 + 3 MiniMIPS Instructions Covered So Far7 Assembly Language Programs7.1 Machine and Assembly LanguagesSymbol Table7.2 Assembler DirectivesComposing Simple Assembler Directives7.3 PseudoinstructionsMiniMIPS Pseudo-instructions 7.4 MacroinstructionsMacro to Find the Largest of Three Values7.5 Linking and Loading7.6 Running Assembler ProgramsInput/Output Conventions for MiniMIPSPCSpim User Interface8 Instruction Set Variations8.1 Complex InstructionsBenefits and Drawbacks of Complex Instructions8.2 Alternative Addressing ModesMore Elaborate Addressing ModesUsefulness of Some Elaborate Addressing Modes8.3 Variations in Instruction FormatsZero-Address Architecture: Stack MachineOne-Address Architecture: Accumulator MachineTwo-Address ArchitecturesExample of a Complex Instruction FormatSome of IA-32’s Variable-Width Instructions8.4 Instruction Set Design and Evolution8.5 The RISC/CISC DichotomyRISC/CISC Comparison via Generalized Amdahl’s LawSome Hidden Benefits of RISC8.6 Where to Draw the LineSome Useful Pseudo Instructions for URISCURISC HardwareJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 1Part IIInstruction-Set ArchitectureJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 2About This PresentationThis presentation is intended to support the use of the textbookComputer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 2005, ISBN 0-19-515455-X. It is updated regularly by the author as part of his teaching of the upper-division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara. Instructors can use these slides freely in classroom teaching and for other educational purposes. Any other use is strictly prohibited. © Behrooz ParhamiEdition Released Revised Revised Revised RevisedFirstJune 2003 July 2004 June 2005 Mar. 2006 Jan. 2007Jan. 2007 Computer Architecture, Instruction-Set Architecture Slide 3A Few Words About Where We Are HeadedPerformance = 1 / Execution time simplified to 1 / CPU execution time CPU execution time = Instructions × CPI / (Clock rate)Performance = Clock rate / ( Instructions × CPI )Define an instruction set;make it simple enough to require a small number of cycles and allow high clock rate, but not so simple that we need many instructions, even for very simple tasks (Chap 5-8)Design hardware for CPI = 1; seek improvements with CPI>1 (Chap 13-14)Design ALU for arithmetic & logic ops (Chap 9-12)Try to achieve CPI = 1 with clock that is as high as that for CPI > 1 designs; is CPI < 1 feasible? (Chap 15-16)Design memory & I/O structures to support ultrahigh-speed CPUsJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 4II Instruction Set ArchitectureTopics in This PartChapter 5 Instructions and AddressingChapter 6 Procedures and DataChapter 7 Assembly Language ProgramsChapter 8 Instruction Set VariationsIntroduce machine “words” and its “vocabulary,” learning:• A simple, yet realistic and useful instruction set• Machine language programs; how they are executed• RISC vs CISC instruction-set design philosophyJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 55 Instructions and AddressingTopics in This Chapter5.1 Abstract View of Hardware5.2 Instruction Formats5.3 Simple Arithmetic/Logic Instructions5.4 Load and Store Instructions5.5 Jump and Branch Instructions5.6 Addressing ModesFirst of two chapters on the instruction set of MiniMIPS:• Required for hardware concepts in later chapters• Not aiming for proficiency in assembler programmingJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 65.1 Abstract View of HardwareFigure 5.1 Memory and processing subsystems for MiniMIPS. Memory up to 2 words 30 Loc 0 Loc 4 Loc 8 Loc m − 4 Loc m − 8 4 B / location m ≤ 2 32 $0 $1 $2 $31 Hi Lo ALU $0 $1 $2 $31 FP arith EPC Cause BadVaddr Status EIU FPU TMU Execution & integer unit Floating- point unit Trap & memory unit . . .. . . (Coproc. 1) (Coproc. 0) (Main proc.) Integer mul/div Chapter 10 Chapter 11 Chapter 12Jan. 2007 Computer Architecture, Instruction-Set Architecture Slide 7Data TypesMiniMIPS registers hold 32-bit (4-byte) words. Other common data sizes include byte, halfword, and doubleword. Byte Hal fword Word Doubleword Byte = 8 bitsWord = 4 bytesDoubleword = 8 bytesQuadword (16 bytes) also used occasionallyHalfword = 2 bytesUsed only for floating-point data, so safe to ignore in this courseJan. 2007 Computer Architecture, Instruction-Set Architecture Slide 8Register ConventionsFigure 5.2 Registers and data sizes in MiniMIPS. Temporary values More temporaries Operands Global pointer Stack pointer Frame pointer Return address Saved Saved Procedure arguments Saved across procedure calls Procedure results Reserved for assembler use Reserved for OS (kernel) $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $30 $31 0 $zero $t0 $t2 $t4 $t6 $t1 $t3 $t5 $t7 $s0


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