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Low- power Data Memory Communication

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Low-power Data Memory Communication forApplication-Specific Embedded Processors Peter Petrov and Alex OrailogluComputer Science & Engineering DepartmentUniversity of California, San Diego(ppetrov,alex)@cs.ucsd.eduABSTRACTWe propose a novel customization methodology for power reduc-tion on the communication link between an embedded processorand its data memory. We target the address bus and show how byutilizing application information about the memory references inthe data intensive program loops, a power efficient address com-munication protocol can be established between the processor coreand the data memory. The data memory controller thus generatesthe addresses for the various data streams with minimal run-timeinformation from the processor engine, achieving significant powerreductions on the address bus. An efficient reprogrammable hard-ware support is presented for enabling the proposed methodology.The experimental results demonstrate the efficacy of the approachfor a set of data intensive applications.Categories and Subject DescriptorsB.3 [Hardware]: Memory structures; B.4 [Hardware]: Input/Outputand Data Communications; C.1 [Computer Systems Organiza-tion]: Processor Architectures; C.3 [Computer Systems Organi-zation]: Special-Purpose and Application-Based SystemsGeneral TermsAlgorithms, Design, Experimentation, Performance1. INTRODUCTIONSignificant advances in VLSI process technology have made theutilization of system-on-a-chip design approaches highly attractive.Cost-efficient products, easy design reuse, and flexible implemen-tation constitute some of the many SOC advantages. Embeddedprocessor cores are being utilized widely in such systems in orderto achieve better time-to-market, lower design cost, and easily re-programmable implementations. However, the increased silicon in-tegration, together with the ever increasing clock frequencies, leadsto proportional increases in terms of power consumption.At the same time, energy dissipation is becoming a prominentcharacteristic for a large number of important applications, such ashand-held and wireless devices. Less energy dissipation leads not This work is supported by NSF Grant 0082325.Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.ISSS’02, October 2–4, 2002, Kyoto, Japan.Copyright 2002 ACM 1-58113-576-9/02/0010 ...$5.00.only to longer battery life, but also enables larger die sizes. Con-sequently, techniques for minimizing system power consumptionare of paramount importance for achieving high product quality.These techniques can be applied on various design abstraction lev-els, from circuit level to system architecture.In a typical DSP or data intensive embedded environment, the in-teraction between the processor core and the on-chip/off-chip datamemory or cache can be significant. Typically, in such environ-ments the local working set is stored in a fast local scratch-padmemory, while a large off-chip data memory is used to bring thedata to be processed from the system’s environment. In the case ofVLIW or SIMD processor engines with multiple load/store units,several data accesses are typically performed within a cycle. Con-sequently, a significant amount of the system power is consumed inthe interaction between processor and data memory subsystem.Hardware/software co-design techniques play a significant rolein building complex SOCs comprising processor cores and dedi-cated ASIC modules. Processor cores are still the most viable so-lution in implementing these complex SOCs if special care is takento obviate the fundamental disadvantages of reduced performanceand high power consumption stemming from their general-purposenature. Customizing the processor microarchitecture to particularapplication-specific needs has been shown to be an efficient tech-nique for boosting processor performance and significantly reduc-ing its power consumption [1].In this paper, we propose an application-specific customizationmethodology for power reduction in the processor’s communica-tion to its data memory. The communication between processorand memory consists of the following operations. A processorload/store unit generates an effective address. This address is sentto the memory subsystem through the address bus along with cer-tain control information. In the case of a store instruction, the datathat needs to be stored is sent along to the memory on the databus. If the transfer is a load, the memory subsystem reads in thedata being referenced by the address and returns it to the proces-sor through the data bus. It is well known that transferring ad-dresses and data on long interconnect busses consumes a significantamount of power, due to the high capacitance of the lines [2].We present a technique for minimizing the traffic on the addressbus to the data memory subsystem. Application-specific informa-tion is statically extracted and dynamically transferred to the datamemory controller prior to the execution of a major loop. Conse-quently, only an insignificant amount of information is transferredfrom the processor core to the data memory controller instead of acomplete effective address, typically 32 bits long. The inherent re-programmability of the proposed approach, extends its applicabil-ity to practically all areas of data-intensive embedded applications.2. RELATED WORKPower optimization techniques at the circuit-level have been thedominant approach in designing energy efficient systems so far [3,4]. However, in recent years, architecture-level approaches haveattained popularity due to their ability to eliminate redundancieson a higher, microarchitectural level, thus resulting in even largerpower optimizations [5].The problem of minimizing the number of transitions on com-munication busses within a microprocessor-based system has beenattacked recently by a number of research groups. The Bus-Invertmethod has been proposed in [6]. In this approach, the bus con-tent is inverted if this leads to a smaller Hamming distance com-pared to the previous value on the bus. An additional bus signalinforms the receiver whether the bus content is inverted or not. Theapproach is applicable to


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