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Paper 44.2 INTERNATIONAL TEST CONFERENCE 0-7803-9039-3/$20.00 © 2005 IEEE 1Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, and Kaushik Roy Dept of ECE, Purdue University, West Lafayette, IN-47907, USA <sm, kang18, mahmoodi, kaushik>@ecn.purdue.edu Abstract The inter-die and intra-die variations in process parameters result in large number of failures in an SRAM array degrading the design yield. In this paper, we propose an adaptive repairing technique for SRAM based on leakage and delay monitoring. Leakage and delay monitoring is used to effectively separate dies with different inter-die Vts from each other. Using the leakage (or delay) monitoring and adaptive body bias, we propose a reliable and self-repairing SRAM which has reduced number of parametric failures under high inter-die and intra-die Vt variations. The proposed self-repairing SRAM improves the design yield by 5%-40% in predictive 70nm technology from BPTM. 1. Introduction Die-to-die and within-die variations in process parameters result in mismatch in the strengths of different transistors in an SRAM cell (Fig. 1), resulting in functional failures (read, write, access and hold failures) [1-2]. The functional failures due to parametric variations (hereafter, referred to as parametric failures) degrades the memory yield (i.e. the number of non-faulty chips) [2]. The principal reason for parametric failures is the intra-die variation in threshold voltage of the cell transistors due to random dopant fluctuations [1-2]. The die-to-die variation in process parameters (say, Vt) also has a strong impact on the failure probability of a cell. In particular, low-Vt dies has a higher probability of read and hold failures while high-Vt dies suffer mostly from access and write failures. Thus die-to-die variations significantly increase the yield degradation. Hence, a self-repairing technique in SRAM that reduces the read/hold failures in low-Vt dies and access/write failures in high-Vt dies can considerably improve yield. This can be achieved by using adaptive repairing technique such as application of Adaptive Body Bias (ABB) [3-6]. Application of Reverse-Body-Bias (RBB) in low-Vt dies increases their Vt thereby reducing possible read/hold failures in SRAM cells. Similarly, application of Forward Body Bias in high-Vt dies decreases their Vt, which reduces the access and write failures in the SRAM cells. However, major obstacle in the application of the adaptive repair techniques in memory is the presence of large intra-die variation. Due to high intra-die variation it becomes difficult to distinguish between a die from low Vt (inter-die) process corner and a die from high Vt (inter-die) process corner. Hence, separation of the dies in different inter-die Vt corners (hereafter, referred to as Vt-binning) is very important for the application of adaptive and self-repair techniques. In this paper, we propose a self-repairing SRAM that successfully detects the inter-die Vt corners and apply a proper body-bias to improve yield. In particular, • We show the application of body-bias in reducing memory failures. • We propose an efficient technique for Vt-binning by monitoring the leakage of a memory array or delay of a ring-oscillator. We show that even under a large intra-die variation monitoring the total memory leakage (or delay of a long inverter-chain) is an effective and reliable technique for separating high-Vt dies from low-Vt ones (i.e. Vt binning). • Finally, using delay and leakage monitoring we propose a reliable and self-repairing SRAM array. In the proposed design using on-chip delay and leakage V R = ‘ 0 ’VDD VL=‘1’BLNL NR PLPRBRWL AXRAXLSubthreshold leakage ( I sub ) Gate leakage ( I gd ) Junction leakage ( I jn ) Fig. 1: SRAM Cell storing “0” at node R. Authorized licensed use limited to: San Francisco State Univ. Downloaded on December 10, 2008 at 22:17 from IEEE Xplore. Restrictions apply.Paper 44.2 INTERNATIONAL TEST CONFERENCE 2monitors, forward or reverse body bias is applied adaptively in an SRAM die depending on its inter-die Vt corner. The proposed design is implemented in BPTM 70nm technology [12] and simulated in HSPICE. Our analysis shows that the self-repair technique in the SRAM improves the yield by 5%-40% depending on the inter-die and intra-die Vt variations. 2. Background: Parametric Failures in SRAM and Effect of Body-Bias 2.1 Parametric Failures in SRAM Cell and Array The intra-die Vt variation ((Vt) due to random dopant fluctuations (RDF) results in failures in SRAM cell. The Vt shifts of the cell transistors due to RDF, can be considered as independent Gaussian random variables with standard deviation given by [1, 7, 8]: 3iox SUB dmVtoxqT N WLWδσε= (1)where, Tox is the oxide thickness, Wdm is the width of the depletion region, and NSUB is the doping concentration in substrate. The parametric failures in an SRAM cell are principally due to [2, 8]: Read Failure - Flipping of the SRAM cell data while reading. The read failure can be reduced by increasing the difference between the voltage rise at the node storing “0” while reading (say, VREAD) and the trip-point of the inverter (VTRIPRD) associated with the node storing “1”. Write Failure – Unsuccessful write to the SRAM cell. Write failure occurs if the node storing “1” cannot be discharged through the access transistors during the word-line turn on time. Access Failure –Access failure occurs if the voltage difference between the two-bitlines (bit-differential) at the time of sense amplifier firing reduces below the offset voltage of the sense-amplifier [15]. Access failure occurs due to the reduction of the bit-line discharging current through the access and pull-down NMOS transistors. Hold Failure - The destruction of the cell data in the standby mode with the application of a lower supply voltage. The hold failure occurs due to high-leakage of the NMOS transistors connected to the node storing “1”. At a lower VDD, due to the leakage of the NMOS, the node storing “1” reduces from VDD (which is enhanced by a weak PMOS). If that voltage becomes lower than the trip-point of the inverter storing “0” the cell flips in the standby mode. If a cell in a


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