New version page

USA EH 334 - Chapter 5 Field-Effect Transistors

Upgrade to remove ads
Upgrade to remove ads
Unformatted text preview:

1Chapter 5Field-Effect TransistorsChapter Goals• Describe operation of MOSFETs and JFETs.• Define MOSFET characteristics in operation regions of cutoff, triode and saturation.• Discuss mathematical models for i-vcharacteristics of MOSFETsand JFETs.• Introduce graphical representations for output and transfer characteristic descriptions of electronic devices.• Define and contrast characteristics of enhancement-mode and depletion-mode MOFETs.• Define symbols to represent MOSFETs in circuit schematics.• Investigate circuits that bias transistors into different operating regions.• MOSFET and JFET DC circuit analysis• Explore MOSFET modeling in SPICEChannel-Length Modulation•As vDSincreases abovevDSAT,the length of the depleted channel beyond pinch-off point, DL, increases and actual L decreases.•iDincreases slightly with vDSinstead of being constant. iD=Kn'2WLvGS−VTN      21+λvDS      λ = channel length modulation parameter2Enhancement-Mode PMOS Transistors: Structure• p-type source and drain regions in n-type substrate.•vGS< 0 required to create p-type inversion layer in channel region• For current flow, vGS< vTP• To maintain reverse bias on source-substrate and drain-substrate junctions, vSB< 0 and vDB< 0• Positive bulk-source potential causes VTPto become more negative3Depletion-Mode MOSFETS• NMOS transistors with• Ion implantation process is used to form a built-in n-type channel in the device to connect source and drain by a resistive channel• Non-zero drain current for vGS= 0; negative vGSrequired to turn device off.VTN≤04Problem-solving Technique :MOSFET DC Analysis• STep1: Requires knowing the bias condition of the transistor such as cutoff or saturation or nonsaturation.• Step2: If the bias condition is not obvious, one must guess the bias condition before analyzing the circuit.• Step3 How can we Guess?(i) Assume that the transistor is biased in the saturation region, which implies that:VGS>VTN, ID>0, and VDS≥VDS(sat)If all the above conditions are satisfied, analyze the circuit using the saturation current voltage relations.(ii) If VGS<VTN, then transistor is probably in cutoff mode.(iii) If VDS<VDS(sat), the transistor is likely biased in nonsaturation region, analyze the circuit using nonsaturationcurrent voltage relations.MOSFET Circuit Symbols•(g) and (i) are the most commonly used symbols in VLSI logic design.• MOS devices are symmetric.•In NMOS, n+region at higher voltage is the drain.•In PMOS p+region at lower voltage is the drainSummary of the MOSFETCurrent-Voltage relationshipTable 5.1MOSFET DC Analysis• The DC circuit analysis is an important part of the design of an amplifier.5Common source circuit with coupling capacitance Cc, which act an an open circuit to the dcDC equivalent circuit.GatePMOS common source circuitIf the device is biased in saturation region6If ID=0 ⇒VDS=5VIf VDS=0 ⇒ ID=VDD/RD=0.25mA78If VGS=0 and drain voltage (VDS) changesPinchoff at the drain


View Full Document
Download Chapter 5 Field-Effect Transistors
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Chapter 5 Field-Effect Transistors and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Chapter 5 Field-Effect Transistors 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?