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Berkeley ELENG 225C - Design and Implementation of a 2-GHz Low-Power CMOS Receiver for WCDMA Applications

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Abstract—This paper describes the design and implementation of a 2-GHz single-chip 0.25-µm CMOS receiver for a custom WCDMA system. A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performance. System specifications are chosen in order to facilitate a low-power highly-integrated implementation. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ∆ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW. I. INTRODUCTION The desire for ubiquitous information access continues to drive the development of applications and services for new wireless systems. The success of these systems will depend heavily on the ability to provide high capacity while maintaining low cost, small form factor and low power consumption in the portable devices. These characteristics may be achieved by adhering to three design strategies. First, at the system level, implementation issues must be considered even during the earliest stages of system definition. Selecting system features which allow for relaxed hardware requirements is paramount to achieving single-chip low-power receiver implementations. Second, efficient implementations require careful partitioning of receiver functions between analog and digital hardware. The rapid improvements in mainstream CMOS technology facilitate the integration of increasingly more functionality onto a single chip. In particular, advanced signal processing algorithms, which are very amenable to low-power digital design techniques, can be used to relax the analog hardware requirements without sacrificing overall system performance. Third, low-power implementation techniques are required to minimize the power consumption of the analog front-end. Despite efforts to simplify the analog hardware, the analog front-end can still dominate overall receiver power consumption. This paper describes the design and implementation of a low-power CMOS receiver which is intended to be used as the analog front-end of a wideband code-division multiple access (WCDMA) system with a carrier frequency of 2 GHz [1]. System specifications are chosen in order to facilitate the use of a direct-conversion architecture, which is amenable to high levels of integration [2]–[4]. All receiver components, including the low-noise amplifier (LNA), frequency synthesizer, mixer and analog-to-digital converter (ADC), are integrated onto a single chip. System specifications are also chosen in order to relax the performance requirements of the analog hardware without significantly degrading overall system performance. Low power consumption is achieved by taking advantage of these relaxed performance requirements as well as by using low-power implementation techniques. Section II provides an overview of the system design, focusing primarily on the trade-offs between analog front-end impairments and system performance. Section III provides a brief description of the system-level simulation framework used to explore these trade-offs, while Section IV describes the implementation of the receiver prototype. Experimental results are presented in Section V, followed by a brief conclusion in Section VI. II. SYSTEM OVERVIEW By taking into account implementation issues during the earliest stages of system definition, system features can be chosen which relax hardware requirements without sacrificing overall performance [5]. Code-division multiple access (CDMA) is chosen as the multiple-access strategy for this system. This direct-sequence spread-spectrum technique is attractive from the system performance perspective since it provides immunity against multipath distortion [6]. In addition, because of the wide bandwidth of the CDMA signal, Design and Implementation of a 2-GHz Low-Power CMOS Receiver for WCDMA Applications Dennis Yee, David Sobel, Chinh Doan, Brian Limketkai, Johan Vanderhaegen, and Robert Brodersen Berkeley Wireless Research Center Dept. of EECS, University of California, Berkeley {dyee, dasobel, cdoan, bnl, jpv, rb}@eecs.berkeley.edu LNA90˚0˚LO (fc)RF FilterIQADCADCRF Input (fc) Fig. 1. Direct-conversion receiver architecture.a simple, direct-conversion architecture can be used for the receiver front-end [7], [8]. This architecture is illustrated in Fig. 1. The RF signal appearing at the antenna is filtered and amplified before being downconverted to baseband along parallel in-phase (I) and quadrature (Q) signal paths. The frequency translation is performed using two mixers and a local oscillator (LO) fixed at the carrier frequency and operating in quadrature. The I and Q baseband signals are then amplified and low-pass filtered prior to analog-to-digital conversion. Because the RF signal is converted directly to baseband, this architecture eliminates all intermediate-frequency components and their associated design challenges, including the image-reject problem. The wideband nature of the desired signal helps mitigate one key problem often associated with direct-conversion architectures: the DC-offset issue. DC offsets are problematic in direct-conversion receivers since the desired signal is downconverted directly to baseband. DC offsets can be caused by systematic offsets in the baseband circuitry, but a potentially more significant source of DC offsets is LO self-mixing. Due to imperfect isolation between the LO and RF ports of the mixer, the LO signal can couple to the RF signal path and mix with itself, resulting in a DC component. For this system, a transmission bandwidth of 32 MHz allows DC offsets to be eliminated with on-chip high-pass filtering. System-level simulations confirm that the degradation in system signal-to-noise ratio (SNR) is less than 1 dB for a high-pass corner frequency of 500 kHz. A similar approach is not feasible for most narrowband signals because a significant portion of the desired signal would be removed. Although a wide transmission bandwidth facilitates the use of a direct-conversion architecture, it also presents design challenges in the ADC due to the high


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