pSeries Overview pSeries Overview and Essential and Essential CommandsCommandsAugust, 2002August, 2002Charles GrasslCharles GrasslIBM Advanced Computing Technology CenterIBM Advanced Computing Technology CenterDesign Design choiceschoicespSeries OverviewpSeries OverviewEssential CommandsEssential CommandsSystem configurationSystem configurationAdministrationAdministrationAgendaAgendaTechnology CollaborationTechnology CollaborationDivisions:Divisions:RS/6000 DivisionRS/6000 DivisionCPU architectureCPU architectureOperating SystemOperating SystemIBM ResearchIBM ResearchComputer ScienceComputer ScienceApplicationsApplicationsCommunicationCommunicationSemiconductorSemiconductorS/390 S/390 Large System ManufacturingLarge System ManufacturingAdvanced Chip TechnologiesAdvanced Chip Technologies1997: Copper Circuitry1997: Copper Circuitry New semiconductor New semiconductor manufacturing manufacturing processprocessCopper has higher Copper has higher electron mobilityelectron mobilitySOISiO21998: Silicon-On-Insulator1998: Silicon-On-InsulatorThin layer of SiOThin layer of SiO22 under silicon surfaceunder silicon surface25% less power at the 25% less power at the same frequencsame frequencyy1-4Advanced Chip TechnologiesAdvanced Chip Technologies2000:2000: low-k dielectric low-k dielectric Shielded Copper Shielded Copper circuitscircuitsFundamental change Fundamental change in materialsin materialsReduces "cross-talk"Reduces "cross-talk"2001: Strained Silicon2001: Strained Silicon material is material is stretched/strainedstretched/strainedSpeeds up flow of Speeds up flow of electronselectronsIntegrated Circuit TrendsIntegrated Circuit TrendsSmaller line widthsSmaller line widthsNearly 0.1 micronNearly 0.1 micronLower voltagesLower voltagesChanging every year!Changing every year!High signal speedHigh signal speedSiOSiO22CopperCopperLow - k dielectricLow - k dielectricMicroprocessor Manufacturing Microprocessor Manufacturing TrendsTrendsDramatic increase in gate count per chipDramatic increase in gate count per chipSize: ~400 sq. mm (20 mm x 20 mm)Size: ~400 sq. mm (20 mm x 20 mm)"Line width" --> 0.11 micron"Line width" --> 0.11 micronHigher gate pitchHigher gate pitchGates are closer togetherGates are closer together~200 million transistors per chip~200 million transistors per chipLithography AdvancesDesign OptionsDesign OptionsLow power chipsLow power chipsSmaller chipsSmaller chipsSimpler circuitsSimpler circuitsHigh performanceHigh performanceLarger on-chip cacheLarger on-chip cache"Wide" CPUs"Wide" CPUsNew designsNew designsMultithreadMultithreadMore CPUs per chipMore CPUs per chip5-8Microprocessor Architecture TrendsMicroprocessor Architecture Trends"Wider" processors (CPUs)"Wider" processors (CPUs)Multiple instruction issueMultiple instruction issuePOWERPOWERAlphaAlphaLong instruction wordLong instruction wordIA-64IA-64MultithreadMultithreadCray MTACray MTAIBM Blue Gene and Blue LightIBM Blue Gene and Blue LightIBM pSeries 660IBM pSeries 660Intel Pentium 4Intel Pentium 4Multiple processors per chipMultiple processors per chipPOWER4POWER4Multiple Processors per ChipMultiple Processors per ChipRetain previous architectureRetain previous architectureBinary compatibilityBinary compatibilityRetain software investmentRetain software investmentPerformancePerformanceParallelismParallelismCapabilityCapabilityCapacityCapacityLimited benefit from "wider" architecturesLimited benefit from "wider" architecturesShared resourcesShared resourcesMemoryMemoryNetwork connectionsNetwork connectionsNew Name Old Name Market CPUiSeries AS400 Commercial RS64pSeries RS/6000, SP TechnicalPOWER3:WH, NH Regatta:POWER4xSeries IA-32 ServerPentium, ItaniumzSeries ES9000 Mainframe RS64IBM Product NamingIBM Product NamingAIX EvolutionAIX EvolutionDerivatives of AT&T 1983AIX V3 - IBM RS/600 POWER Reduced Instruction Set architecture.Adherence to open standards for Unix.1990AIX V564 Bit kernelJFS2 filesystem2001AIX V2 Risc Technology Platform1989AIX V4 -32/64 Bit kernel199764 bit applicationcapabilities9-12AIX CharacteristicsAIX CharacteristicsJournaled file systemJournaled file systemJFS2JFS2File coherencyFile coherencyOther AIX'isms and termsOther AIX'isms and termsLPP - Licensed Program Product (/usr/lpp/...)LPP - Licensed Program Product (/usr/lpp/...)BOS - Base Operating SystemBOS - Base Operating System(bos.rte, bos.up, etc)(bos.rte, bos.up, etc)Administration:Administration:GA - General AcceptanceGA - General AcceptancePTF- A specific software patchPTF- A specific software patchAPAR - A software fault or enhancement APAR - A software fault or enhancement descriptiondescriptionEFIX -An emergency software fix, unvalidatedEFIX -An emergency software fix, unvalidatedSP Evolution:SP Evolution:Pre-POWER3Pre-POWER3SP162.5 MHz POWER1Switch1993SP266 MHz POWER2High Speed Switch1994SP2120 MHz P2SCImproved Switch1996SP2160 MHz P2SC+1997SP24 CPU PowerPC "Silver" node1998Multiple CPUs perNodeSP Evolution:SP Evolution:POWER3 -> POWER4POWER3 -> POWER4SP200 and 222 MHz POWER31998SP375 MHz POWER32000POWER4:Regatta H2001Rebranding:SP--> pSeries2001Large SharedMemory:16 CPU Nodes32 CPUNodesPOWER Processor EvolutionPOWER Processor EvolutionPOWERPOWER21990 1993PowerPC 601P2SC1996PowerPC 604POWER3RS641998POWER42002G3, G4, etc13-16POWER4 RoadmapPOWER4 Roadmap64 bit2001GPCMOS 8S21.3 GHzGQCMOS 9S1.4 - 1.8 GHz2002GRCMOS 9S21.8 - 2.2 GHz2003Workstations (Nodes)(file) ServersLarge ScaleServers"Supercomputers"SP680 44P17044P270F80 M80/H80pSeries (RS6000) FamilypSeries (RS6000) Family640 RegattaFramesFramesFrames contain:Frames contain:NodesNodesSwitchesSwitchesRecent SP configurationFrame ConfigurationFrame Configuration16 Winterhawk2 nodes16 Winterhawk2 nodes64 CPUs64 CPUs96 Gflop/s burst96 Gflop/s burst4 Nighthawk2 nodes4 Nighthawk2 nodes64 CPUs64 CPUs96 Gflop/s burst96 Gflop/s burst1 Regatta node1 Regatta node32 CPUs32 CPUs166 Gflop/s burst166 Gflop/s burstIBMCurrent Regatta configurationIBM IBM17-20Regatta Frame ConfigurationRegatta Frame Configuration1 node per frame:1 node per frame:32 processors ("CPUs")32 processors ("CPUs")Regatta H Regatta H 1.1 GHz1.1 GHzRegatta TurboRegatta Turbo1.3 GHz1.3 GHz16 Processors16 ProcessorsRegatta HPCRegatta HPC1.3 GHz, 1 processor per chip1.3 GHz, 1 processor per chipHigher bandwidth per CPUHigher bandwidth per CPUIBMNodes: WinterhawkNodes: Winterhawk16 nodes per frame16 nodes per frame4 CPUs per node4 CPUs per nodeOperating SystemOperating SystemAIXAIXShared memoryShared