1The The DLXDLXInstructionInstructionSetSetArchitectureArchitectureDLX Architecture OverviewDLX Architecture Overviewn Pronunced deluxn (AMD 29K, DECstation 3100, HP 850, IBM 801, Intel i860, MIPS M/120A, MIPS M/1000, Motorola 88K, RISC I, SGI 4D/60, SPARCstation-1, Sun-4/110, Sun-4/260)/13 = 560 = DLXn Simple Load/Store architecturen Functions that are used less often are considered less critical in terms of performances è Not implemented directly in DLX2DLX Architecture OverviewDLX Architecture Overviewn Three architectural concepts:è Simplicity of load/store ISè Importance of pipelining capabilityè Easily decoded ISn Stuffè 32 GPRs & 32 spFPRs (shared with 16 dpFPRs)è Miscellaneus registersü interrupt handlingü floating-point exceptionsè Word length is 32 bitsè Memory byte addressable, Big Endian, 32-bit addrRegistersRegistersn The DLX ISA contains 32 (R0-R31) 32-bit general-purpose registersn Register R1-R31 are true GP registers (R0 hardwired to 0)n R0 always contains a 0 value & cannot be modifiedè ADDI r1,r0,imm ; r1=r0+immn R31 is used for remembering the return address for JAL & JALR instructions3RegistersRegistersn A register may be loaded withè A byte (8-bit)è An halfword (16-bit)è A fullword (32-bit)BYTE 00 7BYTE 18 15BYTE 216 23BYTE 324 31n Register bits are numered 0-31, from back to front (0 is MSB, 31 is LSB).n Byte ordering is done in a similar mannerRegistersRegistersBYTE 00 7BYTE 18 15BYTE 216 23BYTE 324 31Load/StoreLoad/StoreALU4FloatingFloating--Point RegistersPoint Registersn 32 32-bit single-precision registers (F0, F1, ..., F31)n Shared with 16 64-bit double-precision registers (F0, F2, ..., F30)n The smallest addressable unit in FPR is 32 bitsF0F1F2F3F30F31...F0F2F30...Single-PrecisionFloating PointRegistersDouble-PrecisionFloating PointRegistersMiscellaneous RegistersMiscellaneous Registersn There are 3 miscellaneous registersè PC, Program Counter, contains the address of the instruction currently being retrieved from memory for execution (32 bit)è IAR, Interrupt Address Register, maintains the 32-bit return address of the interrupted program when a TRAP instruction is encountered (32 bit)è FPSR, Floating-Point Status Register, provide for conditional branching based on the result of FP operations (1 bit)5Data FormatData Formatn Byte ordering adheres to the Big Endian orderingè The most significant byte is always in the lowest byte address in a word or halfwordmem[0] ←← 0xAABBCCDDDDCCBBAAAABBCCDD3210Big Endian Little EndianbyteaddressAddressingAddressingn Memory is byte addressableè Strict address alignment is enforcedn Halfword memory accesses are restricted to even memory addressè address = address & 0xfffffffen Word memory accesses are restricted to memory addresses divisible by 4è address = address & 0xfffffffc6Instruction ClassesInstruction Classesn The instructions that were chosen to be part of DLX are those that were determined to resemble the MFU (and therefore performance-critical) primitives in programn 92 instructions in 6 classesè Load & store instructionsè Move instructionsè Arithmetic and logical instructionsè Floating-point instructionsè Jump & branch instructionsè Special instructionsInstruction TypesInstruction Typesn All DLX instruction are 32 bits and must be aligned in memory on a word boundaryn 3 instruction formatè I-type (Immediate): manipulate data provided by a 16 bit fieldè R-type (Register): manipulate data from one or two registersè J-type (Jump): provide for the executions of jumps that do not use a register operand to specify the branch target address7II--type Instructions (1 of 3)type Instructions (1 of 3)n Load/Store (u/s byte, u/s halfword, word)n All immediate ALU operationsn All conditional branch instructionsn JR, JALROpcode0 56rs16 105rd11 155immediate16 3116n Opcode: DLX instruction is being executedn rs1: source for ALU, base addr for Load/Store, register to test for conditional branches, target for JR & JALRII--type Instructions (2 of 3)type Instructions (2 of 3)Opcode0 56rs16 105rd11 155immediate16 3116n rd: destination for Load and ALU operations, source for Store. è Unused for conditional branches and JR and JALRn immediate: offset used to compute the address for loads and stores, operand for ALU operations, sign-ext offset added to PC to compute the branch target address for a conditional branch. è Unused for JR and JALR8II--type Instructions (3 of 3)type Instructions (3 of 3)Opcode0 56rs16 105rd11 155immediate16 3116addi r1,r2,5 ; r1=r2+sigext(5) ; rd=r1, rs1=r2, imm=0000000000000101addi r1,r2,-5 ; r1=r2+sigext(-5); rd=r1, rs1=r2, imm=1111111111111011jr r1 ; rs1=r1jalr r1 ; rs1=r1lw r3, 6(r2) ; r3=Mem[sigext(6)+r2]; rd=r3, rs1=r2, imm=6sw -7(r4),r3 ; Mem[sigext(-7)+r4]=r3; rd=r3, rs1=r4, imm=-7beqz r1,target ; if (r1==0) PC=PC+sigext(target); rs1=r1, imm=target jr r1 ; PC=r1 ; rs1=r1RR--type Instructionstype Instructionsn Used for register-to-register ALU ops, read and writes to and from special registers (IAR and FPSR), and moves between the GPR and/or FPRR-R ALU0 56rs16 105rs211 15516 31rd unused func20 21 25 265 5 6R-R FPU0 56rs16 105rs211 15516 31rd unused func20 21 25 265 6 5add r1,r2,r3 ; rd=r1, rs1=r2, rs2=r3addf f1,f2,f3 ; rd=f1, rs1=f2, rs2=f39JJ--type Instructionstype Instructionsn Include jump (J), jump & link (JAL), TRAP, and return from exception (RFE)n name: 26-bit signed offset that is added to the address of the instruction in the delay-slot (PC+4) to generate the target addressè For TRAP, it specifies an unsigned 26-bit absolute addressOpcode0 56name6 3126j target ; PC=PC+sigext(target)Load & Store InstructionsLoad & Store Instructionsn Two categoriesè Load/store GPRè Load/store FPRn All of these are in I-type formateffective_address = (rs)+sigext(immediate)10Load & Store GPRLoad & Store GPRn LB, LBU, SBn LH, LHU, SHn LW, SWLB/LBU/LH/LHU/LW rd,immediate(rs1)SB/SH/SW immediate(rs1),rdStore Byte (Example)Store Byte (Example); Let r1=9, r2=0xffsb 5(r1),r200 00 00 09r1+0xE0x100xc0x140x80x4? ? ? ?? ? 0xff ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?0x0? ? ? ffr2Data Memory5immediate11Load Byte (Example)Load Byte (Example); Let r1=9lb r3,5(r1)0x100xc0x140x80x4? ? ? ?? ? 0xff ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?0x0ff ff ff ffr300 00 00 ffr300 00 00 09r10xElblbuData Memory+5immediateMove InstructionsMove Instructionsn All of these are in the R-type formatè MOVI2S, MOVS2I: GPR ↔ IARü movi2s rd,rs1 ; rd∈∈SR, rs1∈∈GPRü movs2i
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