View Full Document

Modeling Cache Sharing on Chip Multiprocessor Architectures



View the full content.
View Full Document
View Full Document

34 views

Unformatted text preview:

Modeling Cache Sharing on Chip Multiprocessor Architectures Pavlos Petoumenos 1 Georgios Keramidas 1 H kan Zeffer 2 Stefanos Kaxiras 1 Erik Hagersten2 1 Department of Electrical and Computer Engineering University of Patras Greece ppetoumenos keramidas kaxiras ee upatras gr 2Department of Information Technology Uppsala University Sweden zeffer eh it uu se Abstract As CMPs are emerging as the dominant architecture for a wide range of platforms from embedded systems and game consoles to PCs and to servers the need to manage on chip resources such as shared caches becomes a necessity In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine grain mechanism Our model called StatShare accurately describes the behavior of the sharing threads using run time information reuse distance information for memory accesses and helps us understand how effectively each thread uses its space The mechanism to manage the cache at the cache line granularity is inspired by Cache Decay but contains important differences Decayed cache lines are not turned off to save leakage but are rather available for replacement Decay modifies the underlying replacement policy random LRU to control sharing but in a very flexible and non strict way which makes it superior to strict cache partitioning schemes both fine and coarse grained The statistical model allows us to assess a thread s cache behavior under decay Detailed CMP simulations show that i StatShare accurately predicts the thread behavior in a shared cache ii managing sharing via decay in combination with the StatShare run time information can be used to enforce external QoS requirements or various high level fairness policies 1 Introduction Processor designers are fast moving towards multiple cores on a chip to achieve new levels of performance Most newly released CPUs are chip multiprocessors and all processor vendors offer at least one CPU model of



Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Modeling Cache Sharing on Chip Multiprocessor Architectures and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Modeling Cache Sharing on Chip Multiprocessor Architectures and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?