Ray Fillion, GE Global Research - Slide 1MSE 542Advanced Packaging Technology for Leading Edge Microelectronicsand Flexible Electronics Ray FillionGE Global ResearchRay Fillion, GE Global Research - Slide 2MSE 542Presentation ObjectiveThis presentation will explore advanced packaging solutions for next generation microelectronics in key applications areas. We will look at how semiconductor trends and key market segments are driving advanced microelectronics packaging developments. Finally, we will look at some approaches to and issues with organic and inorganic flexible electronicsRay Fillion, GE Global Research - Slide 3MSE 542GE Global Research Advanced Packaging Technologies• Fine Line Multilayer Flex• Thin Film Passives• Multichip Modules• 3D Electronic Assembly• Chip Scale Packaging• LED PackagingPackaging & Interconnection Development, Prototype and Low Volume Production Fabrication, Assembly and Test Capability.• Power Packaging• Power Overlay Packaging• WBG Packaging • Nano Interconnects• MEMS Packaging• Photonics PackagingRay Fillion, GE Global Research - Slide 4MSE 542Flex CircuitsHigh Speed Digital MCMFloating PadsGRC Advanced Packaging TechnologiesSensor/MEMSRay Fillion, GE Global Research - Slide 5MSE 542Power Converter3-D Micro StackPhotonicsA/D Mixed MCMGRC Advanced Packaging TechnologiesRay Fillion, GE Global Research - Slide 6MSE 542Evolving Microelectronics Technologies:Gordon Moore’s observation 1965, every 18 months:• 2x increase in gate count • 1.5x increase in I/O countStill following Moore’s Law today due to semiconductor trends in:• feature size reduction• innovative structures • supply voltage reductionsRay Fillion, GE Global Research - Slide 7MSE 542The Semiconductor Device Advances• Finer device features: from submicron to nanometer(0.1 – 0.5 µm) (10 – 100 nm)• Higher I/O count: from 100’s of I/O to 1000’s of I/O• Lower Operating Voltage: from 1.5 – 2.5 V to less than 1V• Increased Power Density: from 1 – 10 W/cm2to 20 – 50 W/ cm2• Faster Clock Rates: from 1 – 3 GHz to 3 – 10 GHzRay Fillion, GE Global Research - Slide 8MSE 542These Semiconductor Trends are having significant impact on every aspect of electronic packaging and interconnection• Increasing chip I/O count driving package I/O’s.• perimeter I/O to area array I/O• tighter package I/O pitch• finer substrate/board interconnect density• Increasing chip clock rates driving interconnect.• finer line pitch• lower dielectric constant • lower dielectric losses • Increasing power dissipation driving package designs.• improved interface materials• more complex cooling structuresRay Fillion, GE Global Research - Slide 9MSE 542• Low-cost: <$300 consumer products, micro-controllers, disk drives, displays• Hand-held: <$1,000 battery-powered products, mobile products, hand-held cellular telecommunications, other hand-held products• Cost-performance: <$3,000 notebooks, desktop personal computers, telecommunications• High-performance: >$3,000 high-end workstations, servers, avionics, supercomputers (the most demanding requirements)• Harsh: Under-the-hood and other hostile environments• Memory: DRAMs, SRAMsITRS Roadmap Defines Six Main Market SegmentsRay Fillion, GE Global Research - Slide 10MSE 542Two of These Electronics Market Segments are the Key Driving Forces Behind Today’s Advanced Packaging and Interconnection Technology Advancements:• Hand-held: <$1,000 battery-powered products• small size, mixed technologies, moderate performance• highest volume, most cost driven• Cost-performance: <$3,000 computing• driving high power, high I/O, high speed• large volumes, moderate cost factorsRay Fillion, GE Global Research - Slide 11MSE 542There are four basic elements that define the structure of a microelectronics package:• The electrical connection of the chip to the package• wirebond, solder bump, TAB, adhesives, other• Encapsulation of the chip• underfill, overmold, injection or transfer molding• The structure of the package• ceramic, organic substrates, metal• molded leadframe• The connections of the package to the circuit board• thru-hole, leaded, leadless, array pads, BGA, etc.Ray Fillion, GE Global Research - Slide 12MSE 542We will next look at the basic elements of various microelectronics packages as they evolved over the past few decades with the evolution of the semiconductor device industry.Ray Fillion, GE Global Research - Slide 13MSE 542Standard PTH Electronics Packages (60’s-70’s)Source: KTHDual-in-Line Plated-Through-Hole Packages• Plus: - Robust lead-in-hole attach- low cost package• Negative: - limited to 100 mil pitch- limited to about 64 I/Os- limited PCB densityRay Fillion, GE Global Research - Slide 14MSE 542Leaded SMT Carrier Evolution (70’s – 80’s)Source: KTHSurface Mount Perimeter Leaded Packages• Plus: - tighter lead pitch to 25 mil pitch- higher I/O count to >200- allowed increased PWB density- lead compliance• Negative: - assembly yield; shorts/opens- more costly packageRay Fillion, GE Global Research - Slide 15MSE 542Leaded Carrier EvolutionSource: KTH• molding compound• die attach adhesive• die attach paddle• the silicon chip• the lead frame• wire bonds Schematic of a Plastic Quad Flet Pack (PQFP) with:Ray Fillion, GE Global Research - Slide 16MSE 542Perimeter I/O Package LimitationsAs the high-end semiconductor device I/O count kept increasing to >250, the perimeter leaded carrier ran into physical limits in its lead pitch and package size.Let’s look at how the perimeter package is effected with increasing I/O count.Ray Fillion, GE Global Research - Slide 17MSE 542Perimeter I/O Package Size vs. I/O We fix lead pitch at 1.2 mm (50mil)24 I/O Leaded FPPackage Area = 64 mm2DieDie48 I/O Leaded FP (2x)Package Area = 256 mm2 (4x) Fixing lead pitch drives package size up, severelyAnd not shown because of size!96 I/O Leaded FP (4x) Package Area = 1024 mm2 (16x)Ray Fillion, GE Global Research - Slide 18MSE 542Leaded Package I/O and Size LimitsWe fix package size at 64 mm2 (8 mm x 8 mm) 24 I/O Leaded FP@ 1.20 mm pitch DieDie48 I/O Leaded FP (2x)@ 0.60 mm pitch 96 I/O Leaded FP (4x)@ 0.30 mm pitch DieFixing package size drives lead pitches down severely, to point that they are too costly, have assembly yield and have poor reliable.Ray Fillion, GE Global Research - Slide 19MSE 542Leaded Package I/O and Size LimitsAs I/O