UNIVERSITY OF MASSACHUSETTS Dept of Electrical Computer Engineering Digital Computer Arithmetic CE666 Koren Part 4c 1 ECE 666 Part 4 C Floating Point Arithmetic III Israel Koren Spring 2008 Copyright 2008 Koren Floating Point Adders Addition large number of steps executed sequentially some can be executed in parallel CE666 Koren Part 4c 2 Copyright 2008 Koren Effective Addition Subtraction Distinguish between effective addition and effective subtraction Depends on sign bits of operands and instruction executed Effective addition 1 Calculate exponent difference to determine alignment shift 2 Shift significand of smaller operand add aligned significands The result can overflow by at most one bit position Long postnormalization shift not needed Single bit overflow can be detected and if found a 1 bit normalization is performed using a multiplexor CE666 Koren Part 4c 3 Copyright 2008 Koren Eliminate Increment in Rounding Significand adder designed to produce two simultaneous results sum and sum 1 Called compound adder can be implemented in various ways e g carry look ahead or conditional sum Round to nearest even use rounding bits to determine which of the two should be selected These two are sufficient even if a single bit overflow occurs In case of overflow 1 is added in R position instead of LSB position and since R 1 if rounding needed a carry will propagate to LSB to generate correct sum 1 Directed roundings R not necessarily 1 sum 2 may be needed CE666 Koren Part 4c 4 Copyright 2008 Koren Effective Subtraction Massive cancellation of most significant bits may occur resulting in lengthy postnormalization Happens only when exponents of operands are close difference 1 pre alignment can be eliminated Two separate procedures 1 exponents are close difference 1 only a postnormalization shift may be needed 2 exponents are far difference 1 only a pre alignment shift may be needed CE666 Koren Part 4c 5 Copyright 2008 Koren CLOSE Case Exponent difference predicted based on two least significant bits of operands allows subtraction of significands to start as soon as possible If 0 subtract executed with no alignment If 1 significand of smaller operand is shifted once to the right using a multiplexor and then subtracted from other significand In parallel true exponent difference calculated If 1 procedure aborted and FAR procedure followed If 1 CLOSE procedure continued In parallel with subtraction number of leading zeros predicted to determine number of shift positions in postnormalization CE666 Koren Part 4c 6 Copyright 2008 Koren CLOSE Case Normalization and Rounding Next normalization of significand and corresponding exponent adjustment Last rounding precomputing sum sum 1 selecting the one which is properly rounded negation of result may be necessary Result of subtraction usually positive negation not required Only when exponents equal result of significand subtraction may be negative in two s complement requiring a negation step No pre alignment no guard bits no rounding exact result Negation and rounding steps mutually exclusive CE666 Koren Part 4c 7 Copyright 2008 Koren FAR Case First exponent difference calculated Next significand of smaller operand shifted to right for alignment Shifted out bits used to set sticky bit Smaller significand subtracted from larger result either normalized or requiring a single bit position left shift using a multiplexor Last step rounding CE666 Koren Part 4c 8 Copyright 2008 Koren Leading Zeros Prediction Circuit Predict position of leading non zero bit in result of subtract before subtraction is completed Allowing to execute postnormalization shift immediately following subtraction Examine bits of operands of subtract in a serial fashion starting with most significant bits to determine position of first 1 This serial operation can be accelerated using a parallel scheme similar to carrylook ahead CE666 Koren Part 4c 9 Copyright 2008 Koren Alternative Prediction of Leading 1 Generate in parallel intermediate bits ei ei 1 if 1 ai bi and 2 ai 1 and bi 1 allow propagation of expected carry at least one is 1 Subtract executed by forming one s complement of subtrahend and forcing carry into least significant position carry expected ei ai bi ai 1 bi 1 ei 1 if carry allowed to propagate to position i If forced carry propagates to position i i th bit of correct result will also be 1 If not correct result will have a 1 in position i 1 instead Position of leading 1 either same as ei or one to the right Count number of leading zeros in ei provide count to barrel shifter for postnormalization at most one bit correction shift left needed CE666 Koren Part 4c 10 Copyright 2008 Koren Exceptions in IEEE Standard Five types overflow underflow division by zero invalid operation inexact result First three found in almost all floating point systems last two peculiar to IEEE standard When an exception occurs status flag set remains set until cleared specified result generated Example a correctly signed for division by zero Separate trap enable bit for each exception If bit is on when corresponding exception occurs user trap handler is called Sufficient information must be provided by floatingpoint unit to trap handler to allow taking action Example exact identification of exception causing operation CE666 Koren Part 4c 11 Copyright 2008 Koren Overflow Trap Disabled Overflow exception flag set whenever exponent of result exceeds largest value allowed Example single precision overflow occurs if E 254 Final result determined by sign of intermediate overflowed result and rounding mode Round to nearest even with sign of intermediate result Round toward 0 largest representable number with sign of intermediate result Round toward largest representable number with a plus sign if intermediate result positive otherwise Round toward largest representable number with a minus sign if intermediate result negative otherwise CE666 Koren Part 4c 12 Copyright 2008 Koren Overflow Trap Enabled Trap handler receives intermediate result a divided by 2 and rounded a 192 1536 for single doubleprecision format Chosen in order to translate the overflowed result as nearly as possible to middle of exponent range so that it can be used in subsequent operations with less risk of causing further exceptions CE666 Koren Part 4c 13 Copyright 2008 Koren Example Multiplying 2127 with E 254 in single precision by127 2 overflowed product has E 254 254127 381 after being adjusted by 127 Result overflows E 254 If