A Case Study of Time-Multiplexed Assertion Checking for Post-Silicon Debugging Ming Gao Department of Electrical and Computer Engineering University of California, Santa Barbara Santa Barbara, CA 93106, USA [email protected] Kwang-Ting (Tim) Cheng Department of Electrical and Computer Engineering University of California, Santa Barbara Santa Barbara, CA 93106, USA [email protected] ABSTRACT Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below. In this paper, we present a design-for-debug (DfD) technique – named Time-Multiplexed Assertion Checking (TMAC) -- for post-silicon bug detection and isolation. By instantiating assertion checkers in an on-chip reconfigurable block (either an embedded FPGA block or a spare programmable core) in a time-multiplexed fashion, TMAC enables hardware implementation of a large number of assertion checkers on-chip with a trivial area overhead. In a case study of an H.264 decoder, a TMAC implementation with eighty time-multiplexed assertion checkers are compared with an ASIC implementation with and without dedicated assertion checkers. Experimental results demonstrate that, among those injected bugs that cannot be detected by a comprehensive set of testbenches for the decoder, those eighty hardware assertion checkers can successfully detect 39.4% of these hard-to-detect bugs. With TMAC, the area overhead is only 1.3%. Moreover, TMAC significantly reduces the time and effort for identifying the root causes of these detected bugs. The case study shows that, on average, the TMAC checkers reduces the bug detection latency by 87 times, and the location of the first assertion violation can help quickly localize the faulty design module. Keywords Assertion checker, Post-silicon validation, Time-multiplexed, Design for debug 1. INTRODUCTION Post-silicon validation becomes an irreplaceable step in modern System-on-a-Chip (SoC) design flow due to the inherent limitations of pre-silicon verification methods. Limited by scalability, formal techniques are not feasible for full-chip verification of complex SoC designs. On the other hand, bugs may escape from simulation-based verification as many corner cases could be missed due to the high complexity of full-chip simulation. Moreover, electrical bugs caused by crosstalk, power drops, and design marginalities are much more difficult to address in pre-silicon than post-silicon due to the lack of accurate models. Post-silicon validation complements the limitations of pre-silicon verification. A huge amount of functional tests can be applied at system operational speed. Deep states and corner cases would more likely be exercised and thus there will be a better chance to catch hard-to-detect bugs. However, once a failure is observed, the process of identifying the root cause of the failure is very time-consuming, which could account for about 35% of the chip development cycle [1]. It is expected that the fraction of total chip development time dedicated to post-silicon debugging will continue to grow and will become the dominating factor for time-to-market and the major source for time-to-volume pressure. The poor internal observability is the major source of the difficulties for post-silicon debugging which results in the difficulty in hard-to-propagate bug detection and huge amount of debugging data to dump and analyze. In the bug detection phase, bugs will not be detected until a failure is observed by the system validation testbench. Some bugs can be easily activated but hardly propagated to observation points due to the long propagation path. Some other bugs may be propagated to the system output but left unnoticed by the incomplete testbench. These observability issues reduce the chance and increase the time for detecting these hard-to-detect bugs. In the worst case, these bugs escape to volume products and cause catastrophic failures in the field. In the bug isolation phase which attempts to identify the root cause of a validation failure, scanning-and-dumping internal information followed by offline analysis is a common practice in post-silicon [2]. However, in the system validation environment, the observation points are often far away from the root causes in terms of both time and location. A huge amount of debugging data are required to be scanned out and analyzed to identify a complete error propagation trace. For example, as reported in [2], an exemplary system chip with roughly 200,000 flip-flops running at around 100 MHz easily produces 20,000 gigabits of information per second while at most 320 pins can be used as debug outputs [2]. Dumping these debugging data in real time for offline analysis is infeasible. To improve the internal observability, trace recording triggered by on-chip validation monitors provides a promising solution to reducing the time for post-silicon debugging. On one hand, monitoring internal signals and states of low observability will increase the chance of observing the failures caused by hard-to-detect bugs. On the other hand, the validation monitors act as an intelligent trigger for the trace buffers to record only the most relevant debugging information in the most relevant cycles. The root cause analysis starting from the closest internal observation points will lead to significant reduction in the amount of debugging data and the analysis effort. Many DfD architectures and methodologies have been proposed for on-chip signal probing, debugging information recording, and root cause analysis. For example, DAFCA’s ClearBlue [1] provides a holistic user-defined signal probing and trace buffering infrastructure through RTL instrumentation using distributed reconfigurable logic. Another example is IFRA [3], an efficient trace recording architecture for microprocessors. Note that the 978-1-4244-7806-4/10/$26.00 ©2010 IEEE 90effectiveness of ClearBlue and IFRA highly depends on the population and quality of the on-chip validation monitors which are chosen and designed based on designers’ knowledge. Thus, the design, use, and optimization of on-chip validation monitors are still design-dependent and designer-dependent and addressed by ad-hoc heuristics. Design automation of on-chip validation monitors remains an open research problem. Assertions are suitable candidates of on-chip validation monitors for several reasons. 1) Assertions can detect both design errors and electrical bugs; 2)