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Figure 6 1 Layout of Part of a Programmable Logic Cell Array Configurable Logic Block I 0 Block Interconnect Area Figure 6 2 Configuration Memory Cell Q Q WRITE DATA CONFIGURATION CONTROL Figure 6 3 Xilinx 3000 Series Logic Cell DATA IN DI 0 MUX 1 F DIN G LOGIC VARIABLES A B C D E QX RD M M F COMBINATORIAL FUNCTION G QY G QY 0 MUX 1 M M DIRECT RESET M D Q EC RD 1 ENABLE CLOCK M K M RD 0 INHIBIT GLOBAL RESET QX F M F DIN G ENABLE CLOCK D Q M X CLB OUTPUTS Y Figure 6 4 Combinatorial Logic Options A B A B Any QX Function QY C D E QX F Function QY of 4 C Variables of 4 Variables D QX QX Function QY G of 4 MODE Any Function QY of 5 Variables of 4 Variables FG QX Function QY Variables A B M F U X G Any Any C D E Any F G F MODE FGM E MODE Figure 6 5 Flip flops with Clock Enable D1 EC CLK 0 MUX 1 D Q D1 EC CLK RD Q EC D1 EC Q D CE Q FF Reset Figure 6 6 Parallel Adder Subtracter Logic Cell ci bi Su Ad Su A G B Combinational Logic E QX F ci 1 Carry out D Q CE ai Sum RD Reset K Clock F sum ai ai bi Su ci G ci 1 carry out ai ci ai ci bi Su Figure 6 7 Signal Paths Within Adder Subtracter Logic Cell DATA IN DI 0 MUX F DIN G ci bi LOGIC VARIABLES Su QX A B C D E D Q 1 RD F COMBINATORIAL FUNCTION G QY G QY 0 MUX D Q 1 EC RD 1 ENABLE CLOCK DIRECT RESET K RD 0 INHIBIT GLOBAL RESET ai CLB OUTPUTS F DIN G Ad Su ENABLE CLOCK QX F c i 1 Figure 6 8 Xilinx 3000 Series I O Block Vcc PROGRAM CONTROLLED MEMORY CELLS OUT INVERT 3 STATE OUTPUT ENABLE 3 STATE INVERT SLEW RATE PASSIVE PULL UP T O OUT OUTPUT SELECT D Q FLIP FLOP OUTPUT BUFFER I O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH R CK IK TTL or CMOS INPUT THRESHOLD GLOBAL RESET CK1 PROGRAM CONTROLLED MULTIPLEXER CK2 PROGRAMMABLE INTERCONNECTION POINT or PIP Figure 6 10 Direct Interconnects Between Adjacent CLBs Figure 6 9 General purpose Interconnects CLB CLB CLB CLB Switch Matrix CLB CLB Switch Matrix CLB Switch Matrix CLB Switch Matrix CLB Switch Matrix CLB CLB CLB CLB Switch Matrix CLB CLB Figure 6 11 Vertical and



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